## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Monday, March 28, 2011

### "Time Borrowing" : Static Timing Analysis (STA) basic (Part 2)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

In a ASIC there are majorly two types of component. Flip-flop and other is Latches. Basically Here we will discuss about Latched based timing analysis.
Before this we should understand the basic differences between the latch based design and flip-flop based design.
• Edge-triggered flip-flops change states at the clock edges, whereas latches change states as long as the clock pin is enabled.
• The delay of a combinational logic path of a design using edge-triggered flip-flops cannot be longer than the clock period except for those specified as false paths and multiple-cycle paths. So the performance of a circuit is limited by the longest path of a design.
• In latch based design longer combinational path can be compensated by shorter path delays in the sebsequent logic stages.So for higher performance circuits deisgner are turning to latched based design.
Its true that in the latched based design its difficult to control the timing because of multi-phase clockes used and the lack of "hard" clock edges at which events must occur.

The technique of borrowing time from the shorter paths of the subsequent logic stages to the longer path is called time borrowing or cycle stealing.

 Example of Latched based design.

There are 4 latches (positive level sensitive). L1 and L3 are controlled by PH1 and L2 and L4 are controlled by PH2. G1, G2, G3 and G4 are combinational logic paths. For now assume a library setup time is zero for the latches and zero delay in latch data-path in the transparent mode.
Now if assume that if  designs using edge-triggered flip-flops, the clock period has to be at least 8 ns because the longest path in G1 is 8 ns. Now as the clock pulse is 5ns , there is a voilation at L2. On the other hand, if the design uses latches , L2 latch is transparent for another 5ns and since the eighth (8th) ns is within the enabled period of L2, the signal along path1 can pass through L2  and continue on path2. Since the delay along path2 is 2 ns, which is short enough to compensate for the overdue delay of path1, this design will work properly. In other word we can say that path1 can borrow sometime (3ns) from the path2. Since the sum of path1 and path2 is 10ns, which is the required time of L3, there will be no voilation in either of the Latches.
For the same reason, path3 can borrow some time (1ns) from path4 without any timing violation.

Note: A latch-based design completes the execution of the four logic stages in 20 ns, whereas an edge-triggered based design needs 32 ns.

Lets see this in a more complex design. Its self explanatory.
 Example Of Timing Borrowing
Just wanted to convey here that this Timing borrowing can be multistage. Means we can easily say that for a latched based design,  each executing path must start at a time when its driving latch is enabled, and end at a time when its driven latch is enabled.

Few Important things:
• Time borrowing occur with in the same cycle. Means launching and capturing latches be using the same phase of the same clock. when the clocks of the launching and capturing latches are out of phase, time borrowing is not to happen. Usually it was disabled by EDA tools.

• Time borrowing typically only affects setup slack calculation since time borrowing slows data arrival times. Since hold time slack calculation uses fastest data, time-borrowing typically does not affect hold slack calculation.

Few Important terminology:

Maximum Borrow time:
Maximum Borrow time is the clock pulse width minus the library setup time of the latch. Usually to calculate the maximum allowable borrow time, start with clock pulse width and then substract clock latency , clock reconvergence pessimism removal , library setup time of the endpoint latch.

Negative Borrow time:
If the arrival time minus the clock edge is a negative number, the amount of time borrowing is negative ( in other way you can say that no borrowing). This amount is know as Negative Borrow time.

1. Hi, the example you have provided is an out of phase clock triggered latches. But in "Few Important things" you mentioned time borrowing occur for the same phase of the same clock. Could you please clarify or provide a different example with single clock.

1. Hi,

Its true in both way. means time borrowing can be done when the clocks are out of phase, but that's usually disable by the EDA tools.

So prefered or say recommended thing is: both the clock should be in phase relation.

2. it also confused me, in the example, if L1 & L2 are within the same clock phase, it can not work, right? I don't understand when triggered latch and capture latch are using the same clock, how to borrow? for example, if G1 > 5ns, and CLK1 and CLK2 are both 5ns high in same phase, when signal reaches L2, it is already not enabled.... There must be phase different here then they can borrow, right?

3. I think here Fig1 clock1 and clock2 keep a constant phase difference, so they are called in "in phase".
you could think them just keep a constant clock network delay (skew).

here out of phase means theire phase difference is a variable.

4. YES, The two clocks are out of phase .But In few Important things , they are saying about at the time of borrowing
You can see the time of borrowing clearly in the second figure. All borrowing occurs in the positive cycle. Both phi1 and phi2

2. Hi,

Most EDA tools recommend not using latches, and will issue warning. The same goes to verilog coding guidelines, where latches could cause stuck state machine. Are these the same latches you are referring to??

1. Yes. Latches are not recommended but if you can use timing Borrowing technique, then you can use latches. :)

3. Hi, this is a great website for me ( new bird) to understand the STA concept...i will use cadence P&R tool (EDI), can you please show me how to read and understand the timing report, like skew, setup vio...etc.

Thanks again.

1. I would say that it will be good if you read manual for that. Specifying the tool specific things are out of scope of this series. I can try that later on but right now I am really sorry.

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5. "In other word we can say that path1 can borrow sometime (3ns) from the path2. Since the sum of path1 and path2 is 10ns, which is the required time of L3, there will be no voilation in either of the Latches." --> If path2 were to take 3ns, can path2 borrow 1ns from path3? I am just wondering because it is not explained. Thanks in advance!

1. This comment has been removed by the author.

6. Hi
If the latency in clock cycle increases then will the time period go down ? For your example latency is 2 clock cycle.
suppose path1=2ns path2=8ns then How many clock cycle(latency) is required ?Does borrowing can happen from previous stage in this case ?

Does pulse register can use time borrowing ?
what is the difference between time borrowing and cycle stealing ?

1. I don't think that a previous stage can borrow time. Since, the whole concept behind time borrowing is that the next latch can wait till it's clock is high. So the combinational circuit before it can produce the result when it's high and it can be transferred to next circuit.

7. Hi
tell me how to take timing analysis using mentor graphics tool.what is slack in that report.difference between negative and positive slacks.

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41. Hi Guys,
To understand more about time borrowing in latch based design refer to "http://ohotspot.blogspot.in/2012/09/time-borrowing-and-time-stealing.html" (Understanding “Time Borrowing” in real designs).

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43. The last diagram before "few important things" which is supposed to be self-explanatory is not very clear to me. Can someone explain? Thanks!

44. Also the statement that an edge triggered design will take 32 ns?
I read some other blogs that insert a latch between two edge triggered flops..they explain the concept more clearly.

https://forums.xilinx.com/t5/Technical-Blog/Time-Borrowing-in-Latches/ba-p/651529

1. Thanks Aditya for sharing this.
This forum has explained the concept in simple words.
Do keep sharing such findings.

45. Superb and Excellent,
Everything explained here is really very helpful to understand the STA.
Thanks a lot for explaining in such a way.