## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Wednesday, March 9, 2011

### "Timing Paths" : Static Timing Analysis (STA) basic (Part 1)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

## Static Timing analysis is divided into several parts:

As we have discussed in our last blog (about Basic of Timing analysis that there are 2 types of timing analysis.
• Static Timing Analysis
• Dynamic Timing Analysis.
Note: There is one more type of Timing analysis: "Manual Analysis". But now a days nothing is 100% Manual. Evey thing is more automated and less manual. So that we are not discussing right now.

In this Blog (and few next as a part of this) we will discuss about the Static Timing Analysis. We will discuss Dynamic Timing Analysis later on.Static Timing analysis is divided into several parts as per the above mentioned list.

### Static Timing Analysis:

Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions. It considers the worst possible delay through each logic element, but not the logical operation of the circuit.

In comparison to circuit simulation, static timing analysis is
• Faster - It is faster because it does not need to simulate multiple test vectors.
• More Thorough - It is more thorough because it checks the worst-case timing for all possible logic conditions, not just those sensitized by a particular set of test vectors.
Once again Note this thing : Static timing analysis checks the design only for proper timing, not for correct logical functionality.

Static timing analysis seeks to answer the question, “Will the correct data be present at the data input of each synchronous device when the clock edge arrives, under all possible conditions?”

In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input-independent manner. It locates the worst-case delay of the circuit over all possible input combinations. There are huge numbers of logic paths inside a chip of complex design. The advantage of STA is that it performs timing analysis on all possible paths (whether they are real or potential false paths).
However, it is worth noting that STA is not suitable for all design styles. It has proven efficient only for fully synchronous designs. Since the majority of chip design is synchronous, it has become a mainstay of chip design over the last few decades.

The Way STA is performed on a given Circuit:
To check a design for violations or say to perform STA there are 3 main steps:
• Design is broken down into sets of timing paths,
• Calculates the signal propagation delay along each path
• And checks for violations of timing constraints inside the design and at the input/output interface.

The STA tool analyzes ALL paths from each and every startpoint to each and every endpoint and compares it against the constraint that (should) exist for that path. All paths should be constrained, most paths are constrained by the definition of the period of the clock, and the timing characteristics of the primary inputs and outputs of the circuit.

Before we start all this we should know few key concepts in STA method: timing path, arrive time, required time, slack and critical path.
Let's Talk about these one by one in detail. In this Blog we will mainly Focus over Different Types of Timing Paths.

Timing Paths:

Timing paths can be divided as per the type of signals (e.g clock signal, data signal etc).

Types of Paths for Timing analysis:
• Data Path
• Clock Path
• Clock Gating Path
• Asynchronous Path
Each Timing path has a "Start Point" and an "End Point". Definition of Start Point and End Point vary as per the type of the timing path. E.g for the Data path- The startpoint is a place in the design where data is launched by a clock edge. The data is propagated through combinational logic in the path and then captured at the endpoint by another clock edge.

Start Point and End Point are different for each type of paths. It's very important to understand this clearly to understand and analysing the Timing analysis report and fixing the timing violation.

• Data path
• Start Point
• Input port of the design (because the input data can be launched from some external source).
• Clock pin of the flip-flop/latch/memory (sequential cell)
• End Point
• Data input pin of the flip-flop/latch/memory (sequential cell)
• Output port of the design (because the output data can be captured by some external sink)
• Clock Path
• Start Point
• Clock input port
• End Point
• Clock pin of the flip-flop/latch/memory (sequential cell)
• Clock Gating Path
• Start Point
• Input port of the design
• End Point
• Input port of clock-gating element.
• Asynchronous path
• Start Point
• Input Port of the design
• End Point
• Set/Reset/Clear pin of the flip-flop/latch/memory (sequential cell)

### Data Paths:

If we use all the combination of 2 types of Starting Point and 2 types of End Point, we can say that there are 4 types of Timing Paths on the basis of Start and End point.
• Input pin/port to Register(flip-flop).
• Input pin/port to Output pin/port.
• Register (flip-flop) to Register (flip-flop)
• Register (flip-flop) to Output pin/port

 Timing Path- 4 types of  Data Path

PATH1- starts at an input port and ends at the data input of a sequential element. (Input port to Register)
PATH2- starts at the clock pin of a sequential element and ends at the data input of a sequential element. (Register to Register)
PATH3- starts at the clock pin of a sequential element and ends at an output port.(Register to Output port).
PATH4- starts at an input port and ends at an output port. (Input port to Output port)

### Clock Path:

 Timing Paths- Clock Paths

In the above fig its very clear that for clock path the starts from the input port/pin of the design which is specific for the Clock input and the end point is the clock pin of a sequential element. In between the Start point and the end point there may be lots of Buffers/Inverters/clock divider.

### Clock Gating Path:

Clock path may be passed trough a “gated element” to achieve additional advantages. In this case, characteristics and definitions of the clock change accordingly. We call this type of clock path as “gated clock path”.

As in the following fig you can see that

 Timing Path- Clock Gating path.

LD pin is not a part of any clock but it is using for gating the original CLK signal. Such type of paths are neither a part of Clock path nor of Data Path because as per the Start Point and End Point definition of these paths, its different. So such type of paths are  part of Clock gating path.

### Asynchronous path:

A path from an input port to an asynchronous set or clear pin of a sequential element.

See the following fig for understanding clearly.

 Timing Path- Asynchronous Path

As you know that the functionality of set/reset pin is independent from the clock edge. Its level triggered pins and can start functioning at any time of data. So in other way we can say that this path is not in synchronous with the rest of the circuit and that's the reason we are saying such type of path an Asynchronous path.

Other types of Paths:

There are few more types of path which we usually use during timing analysis reports. Those are subset of above mention paths with some specific characteristics. Since we are discussing about the timing paths, so it will be good if we will discuss those here also.

Few names are
• Critical path
• False Path
• Multi-cycle path
• Single Cycle path
• Launch Path
• Capture Path
• Longest Path ( also know as Worst Path, Late Path, Max Path , Maximum Delay Path )
• Shortest Path ( Also Know as Best Path, Early Path, Min Path, Minimum Delay Path)

### Critical Path:

In short, I can say that the path which creates Longest delay is the critical path.
• Critical paths are timing-sensitive functional paths. because of the timing of these paths is critical, no additional gates are allowed to be added to the path, to prevent increasing the delay of the critical path.
• Timing critical path are those path that do not meet your timing. What normally happens is that after synthesis the tool will give you a number of path which have a negative slag. The first thing you would do is to make sure those path are not false or multicycle since it that case you can just ignore them.
Taking a typical example (in a very simpler way), the STA tool will add the delay contributed from all the logic connecting the Q output of one flop to the D input of the next (including the CLK->Q of the first flop), and then compare it against the defined clock period of the CLK pins (assuming both flops are on the same clock, and taking into account the setup time of the second flop and the clock skew). This should be strictly less than the clock period defined for that clock. If the delay is less than the clock period, then the "path meets timing". If it is greater, than the "path fails timing". The "critical path" is the path out of all the possible paths that either exceeds its constraint by the largest amount, or, if all paths pass, then the one that comes closest to failing.

### False Path:

• Physically exist in the design but those are logically/functionally incorrect path. Means no data is transferred from Start Point to End Point. There may be several reasons of such path present in the design.
• Some time we have to explicitly define/create few false path with in the design. E.g for setting a relationship between 2 Asynchronous Clocks.
• The goal in static timing analysis is to do timing analysis on all “true” timing paths, these paths are excluded from timing analysis.
• Since false path are not exercised during normal circuit operation, they typically don't meet timing specification,considering false path during timing closure can result into timing violations and the procedure to fix would introduce unnecessary complexities in the design.
• There may be few paths in your design which are not critical for timing or masking other paths which are important for timing optimization, or never occur with in normal situation. In such case , to increase the run time and improving the timing result , sometime we have to declare such path as a False path , so that Timing analysis tool ignore these paths and so the proper analysis with respect to other paths. Or During optimization don't concentrate over such paths. One example of this. e.g A path between two multiplexed blocks that are never enabled at the same time. You can see the following picture for this.

 False Path

Here you can see that False path 1 and False Path 2 can not occur at the same time but during optimization it can effect the timing of another path. So in such scenario, we have to define one of the path as false path.

Same thing I can explain in another way (Note- Took snapshot from one of the forum). As we know that, not all paths that exist in a circuit are "real" timing paths. For example, let us assume that one of the primary inputs to the chip is a configuration input; on the board it must be tied either to VCC or to GND. Since this pin can never change, there are never any timing events on that signal. As a result, all STA paths that start at this particular startpoint are false. The STA tool (and the synthesis tool) cannot know that this pin is going to be tied off, so it needs to be told that these STA paths are false, which the designer can do by telling the tool using a "false_path" directive. When told that the paths are false, the STA tool will not analyze it (and hence will not compare it to a constraint, so this path can not fail), nor will a synthesis tool do any optimizations on that particular path to make it faster; synthesis tools try and improve paths until they "meet timing" - since the path is false, the synthesis tool has no work to do on this path.
Thus, a path should be declared false if the designer KNOWS that the path in question is not a real timing path, even though it looks like one to the STA tool. One must be very careful with declaring a path false. If you declare a path false, and there is ANY situation where it is actually a real path, then you have created the potential for a circuit to fail, and for the most part, you will not catch the error until the chip is on a board, and (not) working. Typically, false paths exists

• from configuration inputs like the one described above
• from "test" inputs; inputs that are only used in the testing of the chip,and are tied off in normal mode (however, there may still be some static timing constraints for the test mode of the chip)
• from asynchronous inputs to the chip (and you must have some form of synchronizing circuit on this input) (this is not an exhaustive list, but covers the majority of legitimate false paths).
So we can say that false paths should NOT be derived from running the STA tool (or synthesis tool); they should be known by the designer as part of the definition of the circuit, and constrained accordingly at the time of initial synthesis.

### MultiCycle Path:

• A multicycle path is a timing path that is designed to take more than one clock cycle for the data to propagate from the startpoint to the endpoint.

A multi-cycle path is a path that is allowed multiple clock cycles for propagation. Again, it is a path that starts at a timing startpoint and ends at a timing endpoint. However, for a multi-cycle path, the normal constraint on this path is overridden to allow for the propagation to take multiple clocks.
In the simplest example, the startpoint and endpoint are flops clocked by the same clock. The normal constraint is therefore applied by the definition of the clock; the sum of all delays from the CLK arrival at the first flop to the arrival at the D of the second clock should take no more than 1 clock period minus the setup time of the second flop and adjusted for clock skew.
By defining the path as a multicycle path you can tell the synthesis or STA tool that the path has N clock cycles to propagate; so the timing check becomes "the propagation must be less than N x clock_period, minus the setup time and clock skew". N can be any number greater than 1.

Few examples are
• When you are doing clock crossing from two closely related clocks; ie. from a 30MHz clock to a 60MHz clock,
• Assuming the two clocks are from the same clock source (i.e. one is the divided clock of the other), and the two clocks are in phase.
• The normal constraint in this case is from the rising edge of the 30MHz clock to the nearest edge of the 60MHz clock, which is 16ns later. However, if you have a signal in the 60MHz domain that indicates the phase of the 30MHz clock, you can design a circuit that allows for the full 33ns for the clock crossing, then the path from flop30 -> to flop60 is a MCP (again with N=2).
• The generation of the signal 30MHZ_is_low is not trivial, since it must come from a flop which is clocked by the 60MHz clock, but show the phase of the 30MHz clock.
• Another place would be when you have different parts of the design that run at different, but related frequencies. Again, consider a circuit that has some stuff running at 60MHz and some running on a divided clock at 30MHz.
• Instead of actually defining 2 clocks, you can use only the faster clock, and have a clock enable that prevents the clocks in the slower domain from updating every other clock,
• Then all the paths from the "30MHz" flops to the "30MHz" flops can be MCP.
• This is often done since it is usually a good idea to keep the number of different clock domains to a minimum.

### Single Cycle Path:

A Single-cycle path is a timing path that is designed to take only one clock cycle for the data to propagate from the startpoint to the endpoint.

Launch Path and Capture Path:

Both are inter-related so I am describing both in one place. When a flip flop to filp-flop path such as UFF1 to UFF3 is considered, one of the flip-flop launches the data and other captures the data. So here UFF1 is referred to "launch Flip-flop" and UFF3 referred to "capture flip-flop".

These Launch and Capture terminology are always referred to a flip-flop to flip-flop path. Means for this particular path (UFF1->UFF3), UFF1 is launch flip-flop and UFF3 is capture flip-flop. Now if there is any other path starting from UFF3 and ends to some other flip-flop (lets assume UFF4), then for that path UFF3 become launch flip-flop and UFF4 be as capture flip-flop.

The Name "Launch path" referred to a part of clock path. Launch path is launch clock path which is responsible for launching the data at launch flip flop. And Similarly Capture path is also a part of clock path. Capture path is capture clock path which is responsible for capturing the data at capture flip flop.This is can be clearly understood by following fig.

 Launch Clock Path (Launch Path) and Capture Clock Path (Capture path)

Here UFF0 is referred to launch flip-flop and UFF1 as capture flip-flop for "Data path" between UFF0 to UFF1.So Start point for this data path is UFF0/CK and end point is UFF1/D.

One thing I want to add here (which I will describe later in my next blog- but its easy to understand here)-
• Launch path and data path together constitute arrival time of data at the input of capture flip-flop.
• Capture clock period and its path delay together constitute required time of data at the input of capture register.

Note: Its very clear that capture and launch paths are correspond to Data path. Means same clock path can be a launch path for one data path and be a capture path for another datapath. Its will be clear by the following fig (source of Fig is From Synopsys).

 Same clock path behave like Capture and Launch path for different Data path.

Here you can see that for Data path1 the clock path through BUF cell is a capture path but for Data path2 its a Launch Path.

Longest and Shortest Path:

Between any 2 points, there can be many paths.
Longest path is the one that takes longest time, this is also called worst path or late path or a max path.
The shortest path is the one that takes the shortest time; this is also called the best path or early path or a min path.

In the above fig, The longest path between the 2 flip-flop is through the cells UBUF1,UNOR2 and UNAND3. The shortest path between the 2 flip-flops is through the cell UNAND3.

I have tried my best to capture all the important points related to the Timing Paths. Please Let me know If anything is missing here.

1. Hi sir, if for a certain timing contraint u give for ex: let me say that my clock period is 5ns and if slack is met using synopsys primetime, so can i say my frequency of operation of my whole ckt is 200MHz ??? kindly reply. Thanks

1. Yes. Frequency = 1 / Clock Period

2. Hi,

Fabulous work u r doing. Reaaly the topics covered in this blog are helping me a lot.

Thanks & Regards,
indu.

3. Hi @Samiappa -- you are right.. if slack is meeting.. then you can say .. but still there is a "can".. :) means its not 100% true. There are other factors also. Please see my other blogs for details...

@Indu -- Thanks a lot for such a appreciation.

4. Hi,

I have some doubts in basics of CTS. How can i communicate with you to discuss about my queries? i mailed you yesterday ( mail ID i got from this blog - vlsi.expert@gamil.com ) but the mail delivery is failed. If you don't mind may i have your right mail ID.

I will be more help-full if you can reply to my queries..Since i have more queries i'm asking you to provide any other option which i can communicate with you or do let me know if i shall post my queries here.

Thanks & Regards,
Indu.

1. it's gmail not gamil. This may be the reason because of which your email was not sent

5. Hi Indu,

I am okay with either ways.. means by mail and by posting here...

There is a typo in my mail id ( which you have mentioned here)-- Correct one is
vlsi.expert@gmail.com

6. Hi Expert,

I have sent a mail with list of queries to the above given mail ID.

Thanks a lot for your quick response.

Regards,
Indu.

7. Hi Expert,
These concepts helped me a lot.
Thank you very much

Thanks & Regards
Anil

8. Thanks Anil.

9. Easy to understand and clear...very useful!

10. hello sir,
this is Harish, i just want to say few words abt it. ur blogs are so understandable way to earn knowledge about timing analysis and i recall totally what i know....
and i got some topics from it easily to remember..
so u did a great job..

suggestion: i think its also good if u present this in ppts

11. hi Harish,
First of all. thanks a lot for such compliment. another thing is .. I have these in PPT and uses when ever I have to present anywhere. you can say that its for internal use. :)

1. hello sir,
can u send me those ppts
my email id is meetvatsald@gmail.com

2. hi sir ,
ksiva7079@gmail.com
Thanks ,

3. hi sir,
ksiva079@gmail.com
thanks,

4. Hi Sir, Could you please share the PPT to this email id, harshithajhj@gmail.com.

5. Sir, could you please send me those ppts.
my mail id is shubhamthemotivator@gmail.com

6. Sir , please can u send me those ppts .
My mail id is ambikahunashyal111@gmail.com

12. For multi-cycle paths remember that driving flop/latch holds/keeps output data without changing for more than one cycle, which is the key. Hence there is more time for data to setup to endpoint and more time for the hold race to not violate.

13. Thanks Great work!!!

14. Thanks for sharing your info. I really appreciate your efforts and I will be waiting for your further write ups thanks once again.
Vee Eee Technologies

15. hai sir
this blog was very usefull for my work and easy to understand

great job............

thanks & regards
vimal

16. hai sir
this blog was very usefull for my work and easy to understand

great job............

thanks & regards
vimal

17. sir,
your explanation is good.Thank you this blog cleared most of my doubts regarding timing paths and static timing analysis.

regards
chandrakant

18. sir,
your explanation is good.Thank you this blog cleared most of my doubts regarding timing paths and static timing analysis.

regards
chandrakant

19. thank you friend.

20. Very useful, must read for people like me.
Thanks
Swami

21. Very useful, must read for people like me.
Thanks
Swami

22. The articles are nice .......I am not clear with multicycle path can u provide a figure related to that.....thanks

23. really a nice session for sta terminology...

24. Great Work...

25. Thank you very much for this illustrative explanation on timing analysis ,it is very good for beginner..

26. Hello Sir,

Can you please discuss required time and slack?

27. You should write a book for Standford and IITians. Existing articles and books on this topic shows author themselves do not know what it is. But you explained it perfectly. So you are expert.

28. I usually find the timing concept bit confusing. But reading your blog is just great. It now looks simple and more easy.
Thanks a ton. Keep up the good work.

29. Hello Sir,

Your blog has been very eloquent and information wealthy.
Thanks for such blogs.Please keep up the spirit of writing.

Thanks,
Shivaji.

30. very Good post

31. superb explanation from the expert....

32. what is macro stacking floorplan?.

1. Jigs,

regarding the Floorplan/Placement/Routing - you have to wait little bit. But Sure i will update those info also.

33. thank u 4 clearing my doubts

34. Excellent mr. 'expert' - MCP and shortest and longest path were lucidly described. thanks!

35. Hi,

This is excellent. Please also details about test modes in STA ( scan cap dc, scan cap ac , scan shift, jtag, rambist ).

36. This comment has been removed by the author.

1. Hello sir,

Can you please tell the difference between longest path and critical path with example. I am confused with these paths.

Thanks,
Deepthi

2. You should not be confused. critical path are that path - which has high impact on the design timing. It can be short or may be long path. Point is - if there is any issue in the critical path then you have to fix that one first. you can't even compromise with that path.

Longest path .. means more number of gates and more delay in that path.

37. This comment has been removed by a blog administrator.

38. Very good explanation. :) Good work. Thanks a lot!

39. This comment has been removed by the author.

40. Hello Sir !! here is a link ,the questions are based upon the setup ,hold times prop delays of the system as whole are to be found out .I am clear with finding the setup and hold times as per the method you have said but I have some problem with this .Pl clarify this !
http://web.mit.edu/6.111/www/f2007/tutprobs/sequential.html

41. Hi
Capture clock period and its path delay together constitute required time of data at the input of capture register.
i didn't get this point clearly ..is the capture clock period and clock period same or its the delay of the capture clock path

1. capture clock period == clock period of capture clock. Means there may be scenerion that there are multiple clocks and different clock are driving the capture flipflop and launching FF. So that's the reason I have mentioned specifically "capture clock period "

42. This comment has been removed by the author.

43. Hi,
Thanks for the blog. It's very helpful. But i couldn't understand Multi Cycle Path. Can you update it with using some diagrams so that it can be understood easily

44. hello sir i need basis of static timing verification ....and concept of static timing analysis ....i need overview for about this concepts please upload as soon as possible.......

1. Static Timing Analysis - related a lot of article already present. Please follow other parts of this series.

45. Hello sir,

A great work on STA is given as a nutshell.Thanks a lot.It would be appreciable if you could add details on Statistical Static Timing Analysis (SSTA)also.

1. I will try but It will take some time

46. I finally understood the mumbo jumbo of STA! Thank you so much! :)

47. well explained :-)

48. Hello Sir,
Thank you very much for ur efforts in explaining about STA.
I have a doubt in MCP example explanation were, you have stated
"However, if you have a signal in the 60MHz domain that indicates the phase of the 30MHz clock, you can design a circuit that allows for the full 33ns for the clock crossing, then the path from flop30 -> to flop60 is a MCP (again with N=2)."

why is path between flop30 to flop60 MCP as the launching flop30 operates in slower clock it gives enough time to get sync with flop60 as the next data from flop30 will be launched after two clock cycles at flop60. ( I am taking 30Mhz clock as main clock, as assumed by your statement).

So may be data from flop60 to flop 30 may take 2 cycles as flop60 as to keep its data stable for complete 2 cycles of its clock (60Mhz clk) to sync with flop30.

Please let me know if I have understood something wrong.

Thanks
vijay

49. Sir, Thank you for this blog this is the first time i understood FALSE PATHS correctly

50. why setup time is large compared to hold time????can any one give me answer???

1. Try to figure out once by taking the concept of master Slave flipflop. I think that will help you.

51. hi sir can i get the related papers or pdfs.if so i will give email id

52. I wanted some illustrations or some problems to get perfection.. Can u share d links which provide this..

53. sir i need detailed explanation on critical path analysis

1. Critical path Analysis is a very big topic. Actually It depends how you called a path Critical in your design. Path is critical because it's part of clock path or there is congestion, or setup/holds are violating there.

So please let me know what exactly you want to know.

54. Hi, this is great tutorial, congrats!
I have a question: in the "what is a setup and hold time?" section you have a TpdDIN, this delay is the same than the data path timing?? that you mentioned in previous sections, this TpdDIN delay is the cloud drawing logic that you have in your previous figures?
Thanks

55. This comment has been removed by the author.

56. Sir, in your diagram, where you have flip flops UFF1 to UFF3.

What would happen if the clock period used were shorter than the maximum signal propagation time through the circuit?

Why do electrical signals take time to propagate through combinatorial logic?

57. Hello Sir ,

58. In data path start point,2nd statement should be data pin of ff/latch/memory .
am i correct

59. This is the most well-explained text I have found on STA yet. Very clear and consisely told. Thank you very much for your time and effort on writing this article. As a Computer Engineering student this has helped me a lot with understanding this concept.

60. Awesome stuff

61. in STA description its written that its advantage is that it performs timing analysis for all possible paths(whether real or false) but in false path description its written that timing analysis is not done for false path?? im confused..can anyone plz clarify my doubt..

1. See.. STA can do analysis of any path.
But why do you want to do the analysis on false path ?? So we specify that we don't want to do analysis on false path. If you will do the analysis don't make sense and if there are any violations - then you have to unnecessary waste your time to fix it.
So both statements are correct. :)

62. sir do you have information about to solve problems on combinational circuits delays??
i want more no 0f problems and solutions to calculate max frequency in both combinational and sequential circuits
plz help me sir

63. Hi Expert,
You have done a f=great job..!! Your blog has helped a lot in my interview preparation. But the MCP topic, can you please explain it in more detail, as I am having difficulty in understanding it, esp the 30MHz and 60MHz example.

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66. Your article is very good and useful, thank you very much for this content.
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67. Very good, I think I found the knowledge I needed. I will see and refer some information in your post. thank you.

68. Hello sir,why hold time is less compare to setup time?

69. it's very good, i like it

70. can clock network latency be negative ?? (both case ideal propagated) if yes what does it mean
??
I am running one design while report_timing , (Innovus) i am getting negative network latency .. how it is possible ? In both case , ideal clock and in propagated clock !!

71. Thanks for finally talking about >""Timing Paths" : Static Timing Analysis (STA) basic (Part 1)" <Loved it!

72. What is multi clock timing analysis

73. sir can u please elaborate why clock gating is required

1. for to optimize timing

74. firstly why do we check hold on the same clock edge?

75. hello sir
could you please mail the ppts
my mailid is :kotlomonica@gmail.com

76. u have doe a great job sir

77. hello,
I am bit confused about critical path. When we consider setup critical path should be max delayed path but with respect to hold it should be least delayed path.