## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Friday, April 8, 2011

### "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

Here we will discuss how to calculate the Setup and Hold Violation for a design.

Till now we have discussed setup and hold violation with respect to the single flipflop, now lets extend this to 2 flip flop. In the following fig there are 2 flipflops (FF1 and FF2).

﻿
 Single-Cycle Setup and Hold For Flip-Flops
﻿
Few important things to note down here-
• Data is launching from FF1/D to FF1/Q at the positive clock edge at FF1/C.
• At FF2/D , input data is coming from FF1/Q through a combinational logic.
• Data is capturing at FF2/D, at the positive clock edge at FF2/C.
• So I can say that Launching Flip-Flop is FF1 and Capturing Flip-Flop is FF2.
• So Data path is FF1/C --> FF1/Q --> FF2/D
• For a single cycle circuit- Signal has to be propagate through Data path in one clock cycle. Means if data is launched at time=0ns from FF1 then it should be captured at time=10ns by FF2.
So for Setup analysis at FF2, Data should be stable "Ts" time before the positive edge at FF2/C. Where "Ts" is the Setup time of FF2.
• If Ts=0ns, then , data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=10ns. If data takes too long ( greater then 10ns) to arrive (means it is not stable before clock edge at FF2) , it is reported as Setup Violation.
• If Ts=1ns, then, data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=(10ns-1ns)=9ns. If data takes too long (greater then 9ns) to arrive (means it is not stable before 1ns of clock edge at FF2), it is reported as Setup Violation.
For Hold Analysis at FF2, Data should be stable "Th" time after the positive edge at FF2/C. Where "Th" is the Hold time of FF2. Means there should not be any change in the Input data at FF2/D between positive edge of clock at FF2 at Time=10ns and Time=10ns+Th.
• To satisfy the Hold Condition at FF2 for the Data launched by FF1 at 0ns, the data launched by FF1 at 10ns should not reach at FF2/D before 10ns+Th time.
• If Th=0.5ns, then we can say that the data launched from FF1 at time 10ns does not get propagated so soon that it reaches at FF2 before time (10+0.5)=10.5ns ( Or say it should reach from FF1 to FF2 with in 0.5ns). If data arrive so soon (means with in 0.5ns from FF1 to FF2, data can't be stable at FF2 for time=0.5ns after the clock edge at FF2), its reported Hold violation.
With the above explanation I can say 2 important points:
1. Setup is checked at next clock edge.
2. Hold is checked at same clock edge.
Setup Check timing can be more clear for the above Flip-flop combination with the help of following explanation.

 Setup Check Timing
In the above fig you can see that the data launched by FF1/D ( at launch edge) reaches at FF2/D after a specific delay ( CLK-to-Q delay + Conminational Logic Delay) well before the setup time requirement of Flip-Flop FF2, so there is no setup violation.
From the Fig its clear that if Slack= Required Time - Arrival time < 0 (-ive) , then there is a Setup violation at FF2.

Hold Check timing can be more clear with the help of following circuit and explanation.

﻿
﻿
 Hold Check Timing
﻿
﻿ In the above fig you can see that there is a delay in the CLK and CLKB because of the delay introduced by the series of buffer in the clock path. Now Flip-flop FF2 has a hold requirement and as per that data should be constant after the capture edge of CLKB at Flip-flop FF2.
You can see that desired data which suppose to capture by CLKB at FF2.D should be at Zero (0) logic state and be constant long enough after the CLKB capture edge to meet hold requirement but because of very short logic delay between FF1/Q and FF1/D, the change in the FF1/Q propagates very soon. As a result of that there occurs a Hold violation.
This type of violation (Hold Violation) can be fixed by shortening the delay in the clock line or by increasing the delay in the data path.

Setup and Hold violation calculation for the single clock cycle path is very easy to understand. But the complexity increases in case of multi-cycle path ,Gated clock, Flip-flop using different clocks, Latches in place of Flip-Flop. We will discuss all these later sometime.

#### 58 comments:

1. should not the launch edge be the second rising edge of CLK, since hold checks are done for the same clock cycle?

1. Hi,

I didn't get you question very clearly. Please elaborate it.

2. dear clock checks ideally should be done at the rising or capturing edge of clock b only.. but sir has written and shown in the diagram that the data is arriving at the ff2 d before the clock b and it is in the transition region..which is a hold violation and we l loose data.. at the end sir has written that to avoid it.. either decrease the buffers in the clock path or increase the delay in the data so that the data arrives at or before the capturing edge of the clock b.. just to show the hold violation sir has made the same in the diagram

2. I think there is misprint in hold time analysis

1. can you please let me know what's that misprint?

2. 3rd Paragraph from last. It has" because of very short logic delay between FF1/Q and FF1/D" Its FF2/D

3. thanks man ... You are right.. It should be FF2/D.

4. Thank you so much for the excellent tutorial, sir! Can you please correct the misprint in the original post just in case readers do not see the comment? Thanks again!

5. Could you correct the misprint? Thank you.

3. Thank you very much.

4. hi , do u have nay idea about datapulse violations

5. is setup and hold time for given input slew is constant?

6. i:e
Ts+Th=constant

1. Hi Jigs,

For a particular FF, these numbers are always constant.

2. plz can u explain me ?

7. thank you

8. sir i don't understand.. setup check at next clock edge and hold check at same clock edge.. while launching and capturing edge are different.. plz explain

1. Clock edge at Launching FF - considered as launching edge but when this edge reaches capturing FF, it become Capturing Edge.

Now in setup and hold we are talking every thing on the Capturing FF, means every thing is related to Capturing edge.

I hope you got my point. Still If some confusion, please write in detail about your confusion.

9. Thank you sir, I got your point..

10. Hi VLSI Expert,
You have mentioned that we need to reduce the delay of the clock to avoid the hold time violation right. Could you please clarify me if you are talking about reducing the CLKB clock width?

11. In the Hold Check Timing diagram, it looks like the first transition of FF2/D (1 > 0) happens at about the same time as the first rising edge of CLKB.
So this will result in setup violation (and maybe hold violation too), even before we get to the second rising edge of CLKB.

12. Can you please elaborate why setup check at next clock edge and hold check at same clock edge ?
from CLK1 .. We check both at next clock edge and calculate also like that but why we say diffrently?
Please elaborate

1. Data can arrive at the following flip flop only at the next clock edge. At T1, FF1 generated its output to data D1, whereas FF2 was processing FF1's output to data D0. FF2 will be able to process FF1's output to D1 only at the next clock edge, T2 = T1 + T(clk).

Hold analysis is done only after the data has already arrived, and so naturally for the same clock cycle.

As for the figures posted above, I think the one for Hold Time is perhaps erroneous, since T(launch) and T(capture) must be at the same clock cycle. I've already posted a comment below, highlighting the same. Awaiting yourVLSI's reply!

13. In the Hold Time diagram, the Capture edge has been shown one clock cycle after Launch edge, whereas it should be at the same clock edge (delayed by buffers).

The Set-up Time diagram, too uses the same clock edges, which though, is correct.

1. For the same data Capture and launch edges are always one clock cycle. But for analysis purpose of Hold - you analysis the whole concept at the same edge. I would say - check the pic more closely and you will crack this figure also.

14. Hi,

I am a silent follower of your blog. You are doing a phenomenal service to millions of people through your high caliber VLSI knowledge. If I may request you to write on the following topics, I would be grateful to you,
1. Setup/hold calculation of Multicycle path
a. slow to fast clock path
b. fast to slow clock path

Thanks a lot!
-Mainul

1. Indeed, this set of brilliant engineers managing this blog are the pride of India, and the whole family of electronics engineers!!!

Your request for Multi-cycle Timing explanation is something that many, including me, have been waiting to make!

15. why system goes in metastable state after setup time voilation?

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32. At Hold Check Timing Capture Edge (Rising Edge) of CLKB should to capture the correct value of FF2.D (zero) according to the current figure. There seems to be something wrong with this part of the figure??

1. This figure ... is trying to help you to visualize the reason of the hold Violation.

33. If my chip has a hold violation, can i resolve it by dropping the voltage? I sacrifice frequency potentially, but the delays usually increase with lower voltage?

34. hey have a doubt as we know for flipflop we check the setup at next clock edge and for hold time at same clock edge.

I want to know for latch where will be the setup and hold is checked ( i mean which clock edge )

1. Latch means level-triggered (say 0 level--> 1 level ==> pos-level; 1 level-->0 level==>neg-level);
here the setup check done before the level 1 appears
and the setup check done before the level 1 appears
above mentioned for pos-level
similarly oppose to neg-level

35. Please clear doubt regarding latch setup and hold time claculation

36. The knowledge you share really changes me in life, I sincerely thank you for the things you have done, sure your blog will help more people.

37. I have read through some similar topics! However, your post has given me a very special impression, unlike other posts. I hope you continue to have valuable articles like this or more to share with everyone!
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38. Yes, the article I was looking for. Your article gives me another approach on the subject. I hope to read more articles from you.

39. In the last diagram, shouldn't the FF2Q signal be initially high?

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41. why hold check on same edge?

42. Set up time voilation leads in metastable state
a. always
b. independent
c. never
d. depends