Lots of people asked me to write over timing analysis. Though a lot of material is present but still most of the people are not 100% sure about all these concepts. I am trying to put few of the things here in a simpler language and hope that it will help (beginner and professional).
Please let me know if anybody thinks that I should add few more things here. It’s difficult to put everything in one blog so just consider this as the first part of Timing analysis.
What is Timing Analysis??
Before we start anything at least we should know what exactly we mean by Timing Analysis. Why these days it’s so important?
There are a couple of reasons for performing timing analysis.
- We want to verify whether our circuit meet all of its timing requirements (Timing Constraints)
- There are 3 types of design constraints- timing, power, area. During designing there is a trade-offs between speed, area, power, and runtime according to the constraints set by the designer. However, a chip must meet the timing constraints in order to operate at the intended clock rate, so timing is the most important design constraint.
- We want to make sure that circuit is properly designed and can work properly for all combinations of components over the entire specified operating environment. "Every Time".
- Timing analysis can also help with component selection.
- An example is when you are trying to determine what memory device speed, you should use with a microprocessor. Using a memory device that is too slow may not work in the circuit (or would degrade performance by introducing wait states), and using one that is too fast will likely cost more than it needs to.
So I can say Timing analysis is the methodical analysis of a digital circuit to determine if the timing constraints imposed by components or interfaces are met. Typically, this means that you are trying to prove that all set-up, hold, and pulse-width times are being met.
Note: Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be compromised but not timing!
Types of Timing Analysis:
There are 2 type of Timing Analysis
- Static Timing Analysis
- Checks static delay requirements of the circuit without any input or output vectors.
- Dynamic Timing Analysis.
- verifies functionality of the design by applying input vectors and checking for correct output vectors
The basis of all timing analysis is the clock and the sequential component (here we will discuss with the help of Flip-flop) . Following are few of the things related to clock and flip-flop which we usually wants to take care during Timing analysis.
- It must be well understood parametrically and glitch-free.
- Timing analysis must ensure that any clocks that are generated by the logic are clean, are of bounded period and duty cycle, and of a known phase relationship to other clock signals of interest.
- The clock must, for both high and low phases, meet the minimum pulse width requirements.
- Certain circuits, such as PLLs, may have other requirements such as maximum jitter. As the clock speeds increase, jitter becomes an increasingly important parameter.
- When "passing" data from one clock edge to the other, ensure that the worst-case duty cycle is used for the calculation. A frequent source of error is the analyst assuming that every clock will have a 50% duty cycle.
- All of the flip-flops parameters are always met. The only exception to this is when synchronizers are used to synchronize asynchronous signals
- For asynchronous presets and clears, there are two basic parameters that must be met.
- All setup and hold times are met for the earliest/latest arrival times for the clock.
- Setup times are generally calculated by designers and suitable margins can be demonstrated under test. Hold times, however, are frequently not calculated by designers.
- When passing data from one clock domain to another, ensure that there is either known phase relationships which will guarantee meeting setup and hold times or that the circuits are properly synchronized