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Tuesday, February 21, 2012

Design constraint : Maximum (and minimum) Capacitance


Design Constraints are divided into several parts because it’s really a wide and important topic. I want to discuss this in detail. I have also noticed that lot of information is present in internet but those are bits and pieces. So I am trying my best to cover everything here in a proper way. Let me know in case any of you have any feedback.
  • Part 1a ->  Basics of Design Constraints and Details of "Maximum Transition Time" (max_transition) 
  • Part 1b -> Maximum Fanout Constraint. (max_fanout)
  • Part 1c ->  Maximum (and minimum) capacitance (max_capacitance and min_capacitance)
  • Part 1d ->  Cell degradation (cell_degradation)
In the last part we have discuessed the max_fanout constraints and few details/basic of fanout in general also.
Note: Rest of the parts is still in development.
In the blog we will discuss regarding max_capacitance and min_capacitance constraints.

Maximum (and minimum) capacitance:

  • The maximum (and minimum) total capacitive load that an output pin can drive. 
  • The total capacitance comprises of load pin capacitance and interconnects capacitances. 
  • This info is present in the .lib file. Please see the example with respect to one cell definition.
    •  “max_capacitance” is available only for “output” pins.
  •    Maximum Capacitance:
    •  It is set as a pin-level attribute that defines the maximum total capacitive load that an output pin can drive. 
    • That is, the pin cannot connect to a net that has a total capacitance (load pin capacitance and interconnect capacitance) greater than or equal to the maximum capacitance defined at the pin.
    •  This definition of max capacitance is present in the .lib file as shown in example.
    •  The max_capacitance value can vary with the operating frequency of a cell. (Because the capacitive load vary as per relationship of Xc=1/ωC .)
      •   It may happen that you library is characterize for multiple frequency.
      •  If that‘s the case then you can see one dimensional lookup table with max_capacitance value with each driver pin for each frequency in your .lib file.
    •  Minimum Capacitance:
      •  Some technology libraries specify minimum capacitance. 
      •  The min_capacitance rule specifies the minimum load a cell can drive. It specifies the lower range of loads with which a cell has been characterized to operate.
      • The load driven by a cell should meet the minimum capacitance requirement for that cell. If there is any violation then we can fix it by sizing the driver. 
      • This is more of a modeling constraint and has lower priority in terms of being met.
Now you can also ask why there is need/significance/importance of this parameter?

Simple Ans is – if you have more output capacitance load then it will take more time to charge /discharge to/from  a particular logic level. It means more the delay of that cell is more. So whenever you are characterization libraries then you have to take care about all this parameters. More delay – means you can’t operate this cell for faster chip. More delay mean – there are more possibility of noise. And more important is More Power consumption (dynamic power consumption – we will discuss this in more detail in other blog).

Snapshot of *.lib file (Liberty File)

cell (<cellname>) {
cell_leakage_power : 3.748077e-03;
threshold_voltage_group : "si38p" ;
    area : "8.775" ;
    ….
    abc_cell () {
     
      pin (Z) {
        direction : "output";
        }
      pin (CP) {
        direction : "input";
      }
      pin (D) {
        direction : "input";
      }
      ….
    }
pin (Z) {
      direction : "output";
      related_bias_pin : "VDDB VSSB";
      max_capacitance : 0.334971 ;
     max_fanout : 20 ;
     
     timing () {
        cell_degradation (constraint) {
            index_1 ("1.0, 1.5, 2.0") ;
            values ("1.0, 1.5, 2.0") ;
        }
}
pin (CP) {
      clock : true;
      direction : "input";
      related_bias_pin : "VDDB VSSB";
      rise_capacitance : 0.001733;
      rise_capacitance_range(0.001268,0.002017);
      capacitance : 0.001706;
      fall_capacitance : 0.001680;
      fall_capacitance_range(0.001293,0.001938);
      max_transition : 0.550;
      …..
      }
}

In the next blog we will discuss about the Cell degradation.





Monday, February 20, 2012

Design constraint : Maximum Fanout



7.4a 7.4b 7.4c
Maximum Transition Time Maximum Fanout Maximum And Minimum Capacitance

Design Constraints are divided into several parts because it’s really a wide and important topic. I want to discuss this in detail. I have also noticed that lot of information is present in internet but those are bits and pieces. So I am trying my best to cover everything here in a proper way. Let me know in case any of you have any feedback.

  • Part 1a ->  Basics of Design Constraints and Details of "Maximum Transition Time" (max_transition) 
  • Part 1b -> Maximum Fanout Constraint. (max_fanout)
  • Part 1c ->  Maximum (and minimum) capacitance (max_capacitance and min_capacitance)
  • Part 1d ->  Cell degradation (cell_degradation)
Note: Rest Of the parts is still in development.

In the last blog we have discuessed that Design Constraints are of 2 types:
  • Design Rule Constraints
  • Optimization Constraints
And further Classification of Design Rule Constraints are -- 4 types:
  • Maximum transition time
  • Maximum fanout.
  • Maximum (and minimum) capacitance.
  • Cell degradation
Details of Maximum Transition Time - we have discuessed in last blog. In this part we will discuss about the "Maximum Fanout".


Maximum fanout:

  • The maximum fan-out of an output measures its load-driving capability:
    • It is the greatest number of inputs of gates to which the output can be safely connected.
  • Fanout load is a dimensionless number
  • This info is present in the .lib file. Please see the below snapshot of .lib with respect to one cell definition.
    • “max_fanout” is available only for “output” pins.
  • Whether the circuit is violated or not – calculated as per the following e.g
  • Way to calculate:
    • Sum up all the fanout loads for inputs driven by a pin (driving pin).
    • If the sum of the fanout loads is not more than the max_fanout value, the net driven by X is valid or say not violated , else you have to make changes in your design by adding a buffer or anyother way.

As in the above figure : the max_fanout of X defined aas per the l.lib file is 20. Now if few loads are connected as the output at X then first calculate total fan loads.

So Total Fanout Load is  1.0 +1.0 +3.0 +2.0 = 7.0
Since max_fanout of X > 7.0 - so no violation.

Now let assume that you have set the fanload of OUT1 18.0 ( by using set_fanout_load 18.0)
then Total Fanout Load is 1.0+1.0+18.0+2.0 = 22.0
Since max_fanout of X < 22.0 - so its violation.

Similarly It may be that in you reset the max_fanout of X to 6.0 (by using set_max_fanout 6.0 )
then Toatal Fanout Load is 1.0 +1.0 +3.0 +2.0 = 7.0
Since max_fanout of X < 7.0  - so its violation.

Now same question : What's the need/importance/significance of this parameter (max_fanout) in the design?

Typically manufacturer defines the maximum input current for a particular cell at each logic level. So fanout of a cell A is the max no of input that can be connected to an output (of A) before the current requirement by any of the input exceeds the current that can be delivered by the output while maintain the correct logic level.  ( very big sentance  :)  Read it 4-5 times.. :) ). Actually these are very basics- But its very important to understand this here. :) .. (So I have copied this from Ref1.)

The fan-out depends on the amount of electric current a gate can source or sink while driving other gates.
  • When an output pin is HIGH, the IIH requirements for all receivers must add-up  to be ≤ to the driver's IOH
  • When an output pin is LOW, the IIL requirements for all receivers must add-up  to be ≤ to the driver's IOL.

Given that an output of any logic device can go either HIGH or LOW (High-impedance is not relevant), and hence exhibit either IOH or IOL, respectively, the Fan-Out is the minimum of two ratios:
Fan-Out = min ( IOH/IIH, IOL/IIL )

For example, Input and output currents are the following. Recall that negative current values indicate current flowing out of the gate while positive current values indicate current flowing into the gate:
  • IOH = -400 µA  (i.e., output can source a maximum of 400µA)
  • IOL = 16 µA (i.e., output can sink a maximum of 16µA)
  • IIH = 40 µA (i.e., input can sink a maximum of 40µA)
  • IIL = -1.6 µA (i.e., input can source a maximum of 1.6µA)
Therefore the fan-out is min ( 400/40, 16/1.6) = min (10, 10) = 10. In other words, each gate can drive 10 other gates of same type without getting out of its guaranteed range of operation. If more than 10 gates were connected, the output voltage levels will degrade and the gate will slow down.

What if there were different IC families, where the output was coming from one family while the other inputs related to different logic families? In this case, add IIH for all inputs connected to an output. The sum must be less than the output's IOH. Then add IIL for all inputs connected to an output. The sum must be less than the output's IOL.
The following diagram illustrates the principle of Fan-Out for both HIGH and LOW outputs:

When the NOR gate output is HIGH, the output bin behaves as a current source since IOH flows out of the driver gate and into the set of driven gates. The current IOH equals the sum of all input currents indicated by IIH, flowing into the driven gates. In other words, IOH = ∑IIH.



When the NOR gate output is LOW, the output bin behaves as a current sink since IOL flows into the gate and out of the driven gates. The current IOL equals the sum of all input currents indicated by IIL, flowing out of the driven gates. In other words, IOL = ∑IIL.
For example, IOL (MAX)  = 16mA and IIL (MAX) = -1.6mA (negative current values indicate current flowing out of the gate). Therefore, fan-out is 16/1.6=10:




 Snapshot of .Lib File (Liberty File)


cell (<cellname>) {
cell_leakage_power : 3.748077e-03;
threshold_voltage_group : "si38p" ;
    area : "8.775" ;
    ….
    abc_cell () {
     
      pin (Z) {
        direction : "output";
        }
      pin (CP) {
        direction : "input";
      }
      pin (D) {
        direction : "input";
      }
      ….
    }
pin (Z) {
      direction : "output";
      related_bias_pin : "VDDB VSSB";
      max_capacitance : 0.334971 ;
     max_fanout : 20 ;
     
     timing () {
        cell_degradation (constraint) {
            index_1 ("1.0, 1.5, 2.0") ;
            values ("1.0, 1.5, 2.0") ;
        }
    ....
   }
}

In the next blog (part) we will discuss rest of the Design rule Constraints.




Design constraint : Maximum transition time



7.4a 7.4b 7.4c
Maximum Transition Time Maximum Fanout Maximum And Minimum Capacitance


Design Constraints are divided into several parts Because its really a wide and important topic. I want to discuss this in detail. I have also noticed that lot of information is present in internet but those are bits and pieces. So I am trying my best to cover every thing here in a proper way. Let me know in case any of you have any feedback.

  • Part 1a ->  Basics of Design Constraints and Details of "Maximum Transition Time" (max_transition) 
  • Part 1b ->  Maximum Fanout Constraint. (max_fanout)
  • Part 1c ->  Maximum (and minimum) capacitance (max_capacitance and min_capacitance)
  • Part 1d ->  Cell degradation (cell_degradation)
Note: Rest Of the parts are still in development.

In this blog we will discuss about the
  • Basics of Design Constraints.
  • Classification or types of "Design Constraints".
    • Design Rule Constraints
    • Optimization Constraints
  • Different type of "Design Rule Constraints".
    • Maximum transition time
    • Maximum fanout.
    • Maximum (and minimum) capacitance.
    • Cell degradation
  • Details Of Maximum Transition Time- Design Rule Constraints.
Rest of the Constraints in the next part.

First, we should know the meaning of Constraints. Constraints are type of restrictions. So if you have "N" no of ways to solve a problem, then after applying constraints it may be that there are only few solutions available. Some time it may be that there is no solution and it means the constraints are too much restrictive.
Constraints can be any type – design related, cost related, resource related and market related. But from technically point of view, as an engineer we only deal with technical constraint with in a Chip design cycle.

So Constraints are the instructions that the designer apply during various step in VLSI chip implementation, such as logic synthesis, clock tree synthesis, Place and Route, and Static Timing Analysis.  They define what the tools can or cannot do with the design or how the tool behaves.

Method of exchanging the Constraints across Different tools:  Standard Design Constraint (Synopsys Design Constraint) (SDC) format is the standard method of exchanging the design timing Constraint across different tools. (Please find the Format of SDC in the corresponding Blog).

There are basically two types of Design constraints:

Design Rule Constraints
  • Design rules constraints are defined by the ASIC vendor in the technology library (liberty file *.lib) file (implicit constraints)
  • You cannot discard or override these rules.
  • You can apply more restrictive design rules, but you cannot apply less restrictive ones. This thing you can do with the help of optimization constraints.
  • Design rules constrain the nets of a design but are associated with the pins of cells from a technology library.
  • These constraints can be library specific (common to all the cells defined in that library file) or may be individual cell specific.
 
Optimization Constraints
  • Optimization constraints are explicit constraints (set by the designer).
  • They describe the design goals (area, timing, and so on) the designer has set for the design.
  • They must be realistic.
Design rule constraints:

  • Maximum transition time
    • The transition time of a net is the longest time required for its driving pin to change logic values. Transition time is decided on the basis of rise time and fall time.
    • This constraint (max_transition) is based on the library data. For the nonlinear delay model (NLDM), output transition time is a function of input transition and output load.
    • Way to calculate:
      • CMOS delay model:          Transition Time = Drive R X Load C
      • Non-linear delay model: Transition Time from table lookup and interpolation/extrapolation.
    • You can make the transition time of each net less than the “max_transition” value (defined in the library file) by adding a buffer at the output of driving gate.
    • It can vary with the operating frequency of a cell.
      • Since this parameter is based on rise/fall time and rise/fall time is the time required to charge/discharge input capacitance load of the pin. Now if operating frequency vary, the capacitive load vary as per relationship of Xc=1/ωC .
    • If multiple clocks launch the same paths, the most restrictive value is used.
    • If your design uses multiple technology libraries and each has a different default_max_transition value, synthesis tools uses the smallest max_transition value globally across the design.
    • This info is present in the .lib file (liberty file). Please see the below snapshot of .lib with respect to one cell definition.
      • max_transition is available only for “input” pin.

Now there is one question – What’s the need/importance/significance of this parameter (max_transition) in the design?

Lot of people has different views for this. Like if you will increase the max_transition value then your delay will increase, so library has to characterize for those delay value also and so on. I am not saying that they are not correct but the real concept is different.

Now a day’s power consumption is becoming a major issue. Everyone wants to reduce the power consumption.
Powers are of 2 type- Switching and Leakage power. (Details we will discuss in another blog). Following structure is an inverter consisting of a p-channel to VCC and an n-channel to GND. With low-level input, the p-channel transistor is on and the n-channel is off, causing current to flow from VCC and pulling the node to a high state. With high-level input, the n-channel transistor is on, the p-channel is off, and the current flows to GND, pulling the node low. In both cases, no current flows from VCC to GND. However, when switching from one state to another, the input crosses the threshold region, causing the n-channel and the p-channel to turn on simultaneously, generating a current path between VCC and GND. This current surge can be damaging, depending on the length of time that the input is in the threshold region (Low Level threshold to High Level threshold).
Now, if the transition time is large means length of time to change the logic is large. So both the channel turns on simultaneously more time. Means more Switching power consumption. So library characterization team has to come up with a maximum value of transition time either specific to all cells in a particular library or individual cell.

Inverter


So in short I can say that … When signals switch between low and high levels, there are brief periods of time in which both transistors are on. The duration of this time is proportional to the rise or fall time of the input. Long rise/fall times can cause increased current consumption and/or oscillation of the input buffer. For modern CMOS-based devices, a general rule is to transition between the Vil and Vih thresholds within about 50ns or faster.
Some devices feature a programmable input hysteresis option that allows more tolerance to slow transitioning inputs but that’s the different topic of discussion.

Snapshot of *.lib file (Liberty File)


cell (<cellname>) {
cell_leakage_power : 3.748077e-03;
threshold_voltage_group : "si38p" ;
    area : "8.775" ;
    ….
    abc_cell () {
     
      pin (Z) {
        direction : "output";
        }
      pin (CP) {
        direction : "input";
      }
      pin (D) {
        direction : "input";
      }
      ….
    }
pin (CP) {
      clock : true;
      direction : "input";
      related_bias_pin : "VDDB VSSB";
      rise_capacitance : 0.001733;
      rise_capacitance_range(0.001268,0.002017);
      capacitance : 0.001706;
      fall_capacitance : 0.001680;
      fall_capacitance_range(0.001293,0.001938);
      max_transition : 0.550;
      …..
      }
pin (D) {
      direction : "input";
      related_bias_pin : "VDDB VSSB";
      rise_capacitance : 0.000752;
      rise_capacitance_range(0.000648,0.000960);
      capacitance : 0.000741;
      fall_capacitance : 0.000730;
      fall_capacitance_range(0.000638,0.000875);
      max_transition : 0.800;
      related_power_pin : "VDD";
      related_ground_pin : "VSS";
     …..
}

In the Next part we will discuss maximum Fanout - another type of  Design Rule Constraints.




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