Chapter 1

Chapter 2

Chapter 3

Chapter 4


Introduction

Now in the last blog, we have seen how resistance and capacitance vary with different parameters like Temperature, Width and Thickness of Interconnects/Wire.
In summary:
Parameters

Resistance

Capacitance

Remark
 
Surface

Coupling
 
Temperature ↑

↑




 
Width ↓

↑

↓


 
Thickness ↓

↑



↓
 
Space ↓

No Effect

No effect

↑

Space between same metal plate

Note: The places where “” are present, I will explain those things later on.
Now you can see that in one way or other, the variation in the interconnect resistance and capacitances are correlated since they are dependent upon interconnect’ s physical dimensions.
Now the question is  what’s the significance of these in our design cycle?
Simple ANS:
These interconnect wires are responsible for transferring the signals/power (clock signal or data signal) from one end to other end. So think in this way that if you are travelling from one place to other and there are bumpers in your paths then it will take more time to reach the destination. Similarly, these interconnect capacitances and resistances are like bumpers in the Signals/Power of your circuits.
Effects of these are :
 Impact on delay.
 Energy consumption
 Power distribution
 Introduction of noise sources, which affects reliability
To evaluate the effect of interconnects on design performance we have to model them. For Detail of this topic (Modeling of Interconnects)  Please refer this blog. Delay  "Interconnect Delay Models”: Static Timing Analysis (STA) basic (Part 4b).
Interestingly – In the last paragraph when I have mentioned about the bumpers and all, one question comes in my mind. Is the effect of bumpers always same whether I drive a cycle or a high power 4 wheeler (like trying to compare the resultant bumper’s effect on cycle and 4 wheeler)? And the question is valid. It depends on the reference. A bumper can produce very small resistivity for big vehicle (like heavy truck) but the same bumper can be too resistive for small vehicle (like cycle).
Similar theory is valid in case of Interconnect parasitic also.
A signal path propagation delay in a silicon design consists of two parts
 Gate delay and
 Interconnect delay.
The impact of interconnect parasitic on a path delay may vary significantly from one path to another. For one path, It may be very less because the cell delay is dominating and for other, it may be high because the interconnect delay is dominating. It means, which delay is dominating, plays an important role in our design, in terms of their resultant effect on the performance/accuracy and all.
To find out the impact of resultant delay, we model these with the help of RC corners. Our/designer’s goal to define the RC corner models are to figure out the maximum and minimum value of path delays, i.e. the sum of cell’s delay and interconnects delay in the path.
Now let’s see this in more detail.
There are so many reasons to state that the impacts of parasitic resistance and capacitance may vary dramatically among different paths Because Wires connecting to the gates can be short or long and similarly the numbers of wires connecting to a single gate can be small or large (depends on Fanouts).
Let’s model the wire and nets for better understanding.
In the above figure, we have modeled a driver as a resistor connected in series with the interconnect resistor. Now there may be 4 different scenario based on the fanout of driver and interconnect length.
 Driver Fanout High , Interconnect wire is short
 Driver Fanout Low, Interconnect wire is short
 Driver Fanout High, Interconnect wire is long
 Driver Fanout Low, Interconnect wire is long.
You may be thinking that length of interconnect make sense here because resistance and capacitance of interconnect depends on wire length but why Fanout of driver? From fanout, we can figure out how strong/week is the driver. If fanout is high, means it can drive more load or say long wire. To become high fanout it is necessary that the resistance of the Driver should be less (large fanout > large current > less internal resistance of the driver) and VisaVersa.
So we can say that if fanout is low and interconnect wire is long (Means load for the driver is high), that circuit is not going to work properly (Note: here long wire and low fanout are relative terms to each other) because such driver/gate do not have that much driving strength (current) that it can drive the circuit/gate which is at the other end of the Nets. Most of the signal will drop before reaching the load.
Similarly, if fanout is high and interconnect wire is short (Means load is less), we are not utilizing the resources properly.
We will not study in detail about the above said 2 scenario, so let’s discuss remaining 2 scenarios
 Driver Fanout Low, Interconnect wire is short
 Driver Fanout high, Interconnect wire is long
Let Rd and Rw denotes respectively the “ON resistance” of the output driver and the “wire resistance” and let Cf, and Cw denote the “fanout capacitance” and the “wire capacitance”.
The path delay (td) is expressed as:
td = (Rd + Rw) * (Cf+Cw)
 Scenario 1: (Interconnect wire : short ; Driver’s fanout : small)
 Driver’s effective resistance > typically be much greater than total interconnect resistance. (Rd >>> Rw)
 In the path delay > Driver resistance (Rd) will be dominant.
 Scenario 2: (Interconnect wire : too long ; Driver’s fanout : high )
 Driver’s effective resistance > typically be much small that the interconnect resistance. (Rw>> Rd)
 In the path delay, interconnect resistance (Rw) will be dominant.
So in short, the effect of the bumpers (interconnect delay), depends on the type/characteristic of the vehicle (driverdevice property which is driving the signal on Interconnect). Best/worst case delay of a design does not always occur at the extremes of the interconnect dimensions. (Device properties also play some role here).
Now it looks to me, I have shared enough information which can help you to understand the basics/concepts of RC (interconnects) corners. And it will be very easy for me to ans few of the questions like –
 What are RC corners?
 What’s the significance of these corners?
 How the individual corners effect our design?
(Note: Please let me know in case you have any question/doubt till now. In case, you are not clear, Please go through once again).
Now till now I have talked about the resistance only. So what about the capacitance? As we already know that for a wire if resistance is large then capacitance will be less. So above 2 scenarios, if we want to express only in terms of Interconnect parameters then it can be like this.
 Driver Resistance dominated > means Interconnect resistance is less and it means interconnect Capacitance is large. So in terms of Capacitance we can say Interconnect Capacitance dominated paths.
 Interconnect Resistance dominated paths.
So on the basis of this 2 RC extraction corners are defined.
 Cbest (Also known as Cmin) – minimizes C, maximizes R
 Cworst (Also known as Cmax) – maximizes C, minimizes R
In 90nm technology and above, a timing path is predominantly governed by cell delays. And that’s the reasons only above mentioned 2 RC interconnect corners are sufficient for all the timing analysis. Note here cell delay means product of R and C of the cells. It means R*C of Cells are greater most of the time in comparison to R*C of Interconnect (Remember, I am not talking about individual parameter, I am talking about product of R and C here).
I am sure, you have question that why then we are talking about individual parameter and corners are defined as per that. It’s because individual parameter behaves differently with respect to temperature, voltage and other process parameters. So to study the effect of those variations, we have to study individual parameter and accordingly RC corners are defined.
However below 90nm node, the contribution of interconnect delay in a timing path become significant and the Coupling Cap component (Cc) in net delay can significantly alter slack values at an endpoint of a timing path. So, RC corners have to be split up as per the contribution of each component Ground Capacitance (Cg) and Coupling Capacitance (Cc). So on top of the 2 conventional RC corners Cmax and Cmin, foundry came up with 2 more RC corners.
 RC best (also known as XTALK corner)  Cc is max , Cg x R is min
 RC worst (also known as Delay corner)  Cc is min ,Cg x R is max
So we can say that there are overall 5 parasitic corners.
 Cbest
 Cworst
 RCbest
 RCworst
 Typical
Few definitions/information for every corner based on experience are…
Cbest:
 It has minimum capacitance. So also known as Cmin corner.
 Interconnect Resistance is larger than the Typical corner.
 This corner results in smallest delay for paths with short nets and can be used for minpathanalysis.
Cworst:
 Refers to corners which results maximum Capacitance. So also known as Cmax corner.
 Interconnect resistance is smaller than at typical corner.
 This corners results in largest delay for paths with shorts nets and can be used for maxpathanalysis.
RCbest:
 Refers to the corners which minimize interconnect RC product. So also known as RCmin corner.
 Typically corresponds to smaller etch which increases the trace width. This results in smallest resistance but corresponds to larger than typical capacitance.
 Corner has smallest path delay for paths with long interconnects and can be used for minpathanalysis.
RCworst:
 Refers to the corners which maximize interconnect RC product. So also known as RCmax corner.
 Typically corresponds to larger etch which reduces the trace width. This results in largest resistance but corresponds to smaller than typical capacitance.
 Corner has largest path delay for paths with long interconnects and can be used for maxpathanalysis.
Typical:
 This refers to nominal value of interconnect Resistance and Capacitance.
So you may have noticed that there are 2 types of parasitic one is Cbased and other is RCbased. In Cbased C means worst and best case capacitance but in RCbased RC means worst and best case R with adjustment in C towards worst or best but keeping the process planar. Based on the experience it was found that Cbased extraction provides worst and best case over RC for internal timing paths because Capacitance dominates short wire. However for large design, interblock timing paths were often worst with RC worst parasitic since R dominates for long wires.
Note: No corner guarantees min or max delay for an arbitrary transistor driving an arbitrary wire topology
With the help of below picture, you can easily understand what I am trying to tell you.
In the next blog, I will share more information about the parasitics corners from foundry point of view. In the sence, How metal thickness / Width / Space and all varies and how the foundry provides the data.