## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## 5 Steps to Build Career in VLSI

So many questions on the topic “How to Build Career in VLSI/Semiconductor Industry” ! So, I am composing 5 Steps to build career in this field. It's based on my experience.

Step No 1: Concept building + Basic knowledge Building:

Concepts/Basics are most important for this field. If you are from Electronics background or From Computer Background, then you should have in-depth understanding of the following topics. Note: Few topics are not required for CS students and same for Electronics students.
• CMOS Design + functionality + characteristics  (Electronic –Must have, CS – Good to have)
• Still in several colleges BJT taught in detail and only a small unit regarding the CMOS, so if that’s the case, please pick few good books for basic understanding of CMOS + read different articles from Internet.
• CMOS design
• Different CMOS capacitance + Resistance Concepts
• Stick diagram
• Fabrication process
• Flip-flops  (Electronics – Must Have , CS – Should Have)
• Flips-flops are part of Digital Design in the B.E but these are basic building block of any VLSI design. So we have to be more clear and through about this topic.
• Functionality of Edge and Level Triggered Flip-flop/Latches
• Timing Concepts in case of Flip-flops + Sequential Circuits  (Electronic –Must have, CS – Good to have)
• Setup/Hold/Recovery/Removal concepts
• Different Clock related concepts
• Slew
• Combinational Circuits Concepts: (Electronics + CS – Must have)
• Delay Concepts (Different type of Delays)
• Propagation Delay /Transition Delay
• Cell Delay /Net Delay/Stage Delay etc
• Building different Combinational circuits using different type of GATES.
• Programming / Scripting Knowledge (Electronics – Good to have, CS – Must have)
• VHDL/Verilog
• These are 2 of the few known languages. Knowledge of these can help you in front-end side of VLSI.
• But these are not necessary but it can be an added advantage.
• Perl/TCL scripting
• These are scripting language which is very popular in the Semiconductor industry.
• UNIX based different scripting knowledge.
• C/C++ programming (Electronics – Good to have, CS – Must have)
• This will help you to enter in the development of EDA tools. Few people don’t consider this as VLSI industry, but for me, we can’t separate EDA from VLSI.
• C/C++ programming along with good understanding in Digital Domain is very good combination from skill point of view

Step No 2: Short Term Courses / Certification During or After the Engineering Degree.

It is very well know way in the Software field. During the study, students learn different programming languages and complete few of the Short term courses for increasing their knowledge which is not present or briefly covered in the college curriculum. Same pattern we can apply for the Semiconductor field.
I agree that there are very few institutes in the market which conducted such type of courses and if there are any, they are 2 costly. But still sometime it’s worth.
If you are looking for something while studying then maybe you should not worried about the certificate, always knowledge speaks more then certificates. Certificates may help you during the screening of your profile (Note: Even this is not necessary) but knowledge is something which can help you to crack any interview or written test. So if you can get the knowledge somehow from your senior’s experience + books + internet, then it’s the cheapest and best way. :)
If you have time and money, you can join any good institute. Usually most of the institutes offer a certificate course of full time 6-8 months and for that they usually conduct entrance exams. These institutes also assist in the placements in different companies.
2 of the Indian well known Institutes are:

Step No 3: Master Degree from Reputed College/Universities

I am considering/assuming that the candidates already have an Engineering Degree and they have tried STEP no 1 and 2 (partially). (Note: You can try this option even before trying for 1st and 2nd option but my recommendation to follow mentioned sequence). You can go for VLSI specialized MS/Mtech program. Different Universities are offering such courses, so candidate can try for that also.
Again, during the Master degree, you have to build your concepts and now you have to learn VLSI design flow. Work on the different EDA tools + VLSI concepts. Few of them are
• EDA tools:
• Frontend Tools + Language: Verilog/VHDL, HSPICE, Netlist Simulator, Design Compiler
• Backend Tools: Synopsys (ICC, Primetime , Starrcxt), Cadence (Encounter, QRC), Mentor (Caliber)
• VLSI concepts:
• RTL synthesis
• Layout, Routing , Timing , CTS, Placement

If you are doing any specialized master program then you have to make sure that either your internship or Final semester project should be related to VLSI design where you design a particular circuit from scratch. It will be your main project which can play an important role in your interview. It will be count as your experience and everyone is going to ask the challenges and learning during this project. So it should be real and worth for the master’s program.
Few of the Indian Universities are:

For most of these universities, you have to clear their specific entrance tests and some time interview also. In the entrance test, basically they will check your basics and knowledge.
These universities also assist in the placements in different companies.

Step No 4: Internship / Project Trainee.

It’s not required that you always look for full time jobs especially in this field. Several companies hire candidates as “Intern/Project Trainee” for 6 month / 1 year to evaluate the candidate’s skills and his/her problem solving skills. I would say that’s the best way to show them how worth are you for the company!
Even if they will not convert you into full time employee, the experience you gain on the live project (which you will handle during your internship), will help you in other company’s interview.

Step No 5: Keep Trying and Keep Patience.

I am not writing too much in this section because it’s self explanatory. But Frankly speaking, Because of “Step No 5” – I am here writing this post. And still I am following this step.

Final “Key Words” from the Author:
Sometime, even after following above mentioned steps, students may not get entry into the VLSI field. I would say “no need of worry”. Always try to figure out the reason of failure in each step and try to full fill them and make them your strength. I never come across to any person, who has knowledge + Brand Name + Passion + Dedication + focused and still out of his/her dream field. As per my understanding below are the % distributions of failure.
• 50% of the time – They (candidates) are lacking in the basics and fundamentals,
• 30% of time – They don’t have favorable  attitude ( usually judged by their seriousness in their different projects + past experiences + their passion + dedication)
• 10% of time – Not having Good/Known Brand Name (College / Universities Name).
• 10% of time – “Give Up” because of struggle/challenges you are facing.

I am not saying it’s very easy to enter in this field but believe me it’s not difficult also. Just follow above steps (where the first step is more important) and keep trying and keep patience.

Best of Luck for everyone’s bright future…

## Friday, January 10, 2014

### 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

### 10 Ways to fix SETUP and HOLD violation:

Till now, We have discussed basic concepts of fixing the Setup and Hold violation which include
• Different formulas + explanation to identify the type of violation in design.
• How to fix those violations?
• Different methods of Increasing and Decreasing the Delay in the circuit to fix these type of violations?
And Now it’s the time to list down different methods to fix these violations. I have also explained in brief each and every method, which also referring previous post for reference. One point to remember here that Fixing the Setup and Hold Violation are reverse in nature. All the methods which are applicable to fix one type of methods , hold true and can be apply to fix other type of if we will do the opposite thing. E.g - if setup can be fix by adding 1 buffer in some path then Hold can be fix by removing buffer in that path. (You will see these things below in the post)

In the last you will also find DOs and DON'Ts and recommended approach to fix these violations. These Recommendations helps designer in reducing iteration and fix the violations fast.

#### 8 Ways To Fix Setup violation:

Setup violations are essentially where the data path is too slow compared to the clock speed at the capture flip-flop. With that in mind there are several things a designer can do to fix the setup violations.

Method 1Reduce the amount of buffering in the path.
• It will reduce the cell delay but increase the wire delay. So if we can reduce more cell delay in comparison to wire delay, the effective stage delay decreases.

Method 2 : Replace buffers with 2 Inverters place farther apart
• Adding 2 inverters in place of 1 buffer, reducing the overall stage delay.
• Adding inverter decreases the transition time 2 times then the existing buffer gate. Due to that, the RC delay of the wire (interconnect delay) decreases.
• As such cell delay of 1 buffer gate ≈ cell delay of 2 Inverter gate
• So stage delay (cell delay + wire delay) in case of single buffer < stage delay in case of 2 inverter in the same path.
• You will get the clear understanding by following figure and you can refer the first post to understand how transition time varies across the wire.

Method 3 : HVT swap. Means change HVT cells into SVT/RVT or into LVT.
• Low Vt decrease the transition time and so propagation delay decreases.
• HVT/NVT/LVT type cells have same size and pin position. In both leakage current and speed, LVT>NVT>HVT. So replace HVT with NVT or LVT will speed up the timing without disturb layout.
• Negative effect: Leakage current/power also increases.

Method 4 : Increase Driver Size or say increase Driver strength (also known as upsize the cell)
• Explained the basic and details in the previous post
• Note: Normally larger cell has higher speed. But some special cell may have larger cell slower than normal cell. Check the technology library timing table to find out these special cells. Increasing driver is very commonly used in setup fix.
• Negative effect: Higher power consumption and more area used in the layout.
• I have notice one explanation in book <book name>. I am copying and pasting (not 100%) that here because I like that one. J Marked the important part by Bold.
• The basic layout technique for reducing the gate delay consists in connecting MOS devices in parallel.
• The equivalent width of the resulting MOS device is the sum of each elementary gate width. Both nMOS and pMOS devices are designed using parallel elementary devices.
• Most cell libraries include so-called x1, x2, x4, x8 inverters.
• The x1 inverter has the minimum size, and is targeted for low speed, low power operations.
• The x2 inverter uses two devices x1 inverters, in parallel. The resulting circuit is an inverter with twice the current capabilities. The output capacitance may be charge and discharged twice as fast as for the basic inverter (see below figure), because the Ron resistance of the MOS device is divided by two. The price to pay is a higher power consumption.
• The equivalent Ron resistance of the x4 inverter is divided by four.
• The clock signals, bus, ports and long wires with severe time constraints use such high drive circuits.

Method 5 : Insert Buffers
• Some time we insert the buffer to decrease over all delay in case of log wire.
• Inserting buffer decreases the transition time, which decreases the wire delay.
• If, the amount of wire delay decreases due to decreasing of transition time > Cell delay of buffer, over all delay decreases.
• Negative Effect: Area will increase and increase in the power consumption.

Method 6 : Inserting repeaters:
• Concepts of Repeaters are same as I have discussed in “Inserting the Buffer” (above point). Just I am trying to explain this in a different way but the over concept are same.
• Long distance routing means a huge RC loading due to a series of RC delays, as shown in figure. A good alternative is to use repeaters, by splitting the line into several pieces. Why can this solution be better in terms of delay? Because the gate delay is quite small compared to the RC delay.

• In case of Interconnect driven by a single inverter, the propagation delay become
• Tdelay= tgate+ nR.nC = tgate + n­2RC
• If two repeaters are inserted, the delay becomes:
• Tdelay=tgate (delay of inverter) + 2tgate (delay of repeater) +3RC = 3tgate + 3RC
• So you can see how RC delay is impacting in case of non-repeater in the circuit.
• Consequently, if the gate delay is much smaller than the RC delay, repeaters improve the switching speed performances, at the price of higher power consumption.
• Below figure helps you to understand the practical use of this.

Method 7 : Adjust cell position in layout.
• Let’s assume there are 2 gate (GATE A and GATE B) separated by 1000um. There is another GATE C placed at the distance of 900um from GATE A.
• If we re-position the GATE C at 500um from GATE A (center of GATE A and B), overall delay between GATE A and B decreases.
• You will get the clear understanding by first post and the following diagram.
• Note: The placement in layout may prevent such movement. Always use layout viewer to check if there are any spare space to move the critical cell to an optimal location.

Method 8 : Clock skew:
• By delaying the clock to the end point can relax the timing of the path, but you have to make sure the downstream paths are not critical paths.
• Related to clock skew basic – I will discuss that in SI section.

### 2 Ways to Fix Hold Violations:

Hold violation is the opposite of setup violation. Hold violation happen when data is too fast compared to the clock speed. For fixing the hold violation, delay should be increases in the data path.
Note: Hold violations is critical and on priority basis in comparison are not fixed before the chip is made, more there is nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be reduced.
The designer needs to simply add more delay to the data path. This can be done by

Method 9 : By Adding delays.
• Adding buffer / Inverter pairs /delay cells to the data path helps to fix the hold violation.
• Note: The hold violation path may have its start point or end point in other setup violation paths. So we have to take extra care before adding the buffer/delay.
• E.G. if the endpoint of hold violation path has setup violation with respect to some other path, insert the buffer/delay nearer to start point of hold violation path. Else the setup violation increases in other path.
• if the start point of hold violation path has setup violation with respect to some other path, insert the buffer/delay nearer to end point of hold violation path. Else the setup violation increases in other path.
• I am sure you may be asking what is this and why?
• From below figure, you can also conclude that don’t add buffer/delay in the common segment of 2 paths (where one path has hold violation and other setup violation).

Method 10 : Decreasing the size of certain cells in the data path.
• It is better to reduce the cells closer to the capture flip flop because there is less likely hood of affecting other paths and causing new errors.

Note: Following points are recommended while fixing setup and hold violations.
• Make modification to the data path only.
• Adjusting register location or removing/adding buffers to the clock path will fix the violation that but it may cause more violations for some other paths which may not present before.
• First try to fix setup violation as much as possible. Then later on start fixing hold violation.
• In general, hold time will be fixed during back-end work (during PNR) while building clock tree. If u r a front-end designer, concentrate on fixing setup time violations rather than hold violations.
• Fix all the hold violation, if you have to choose between setup and hold.
• If a chip is done with some setup violations it can work by reducing the frequency.
• If a chip is done with hold violations, we have “JUST DUMP” the chip.

## Wednesday, January 8, 2014

### Effect of Threshold voltage: Static Timing Analysis (STA) Basic (Part-7c)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

#### Effect of Threshold voltage on the propagation delay and transition delay:

If you will see the below equations – I am sure you can easily figure out how threshold voltage effect the cell delay. (Note: Below Resistance formula is with respect to NMOS. You can derive similar formula for PMOS also (Just replace subscript “n” with “p” J ).

From above equation we have following points
• On Resistance of MOS is inversely proportional to the “VDD-VTn” (where VTn is Threshold Voltage).
• Decreasing the threshold voltage (LOW VTn) increases “VDD-VTn” for constant VDD.
• Increasing “VDD-VTn” means decreasing “On Resistance” Rn.
• Decreasing Rn Ã  RC decreases.
• Means large Driving capability (Ability to source or sink current)
• Decrease the time to charge the output load (capacitance) (Consists of  source/drain capacitance of the driving gate, the routing capacitance of wire, and the gate capacitance of the driven gate) **
• Means “Output Transition time of Gate A” and “Input Transition time for Gate B” decreases.
• Decreasing the transition time means decreases the propagation time.

So we can say that…
"Delay can be reduced by using low Vt cells, but the cost paid is high leakage power"
Direct effect is that low Vt cells are often more leaky i.e. leakage power increases.
If still you have any confusion below diagram should clarify your doubts.

I hope above diagram should clear your doubts about the effect of Threshold voltage on Delay.

In the next post we will summarize/list down all the methods of fixing the setup and hold violations.