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Tuesday, November 24, 2015

DIGITAL BASIC : Sequential Circuit


In the combinational circuits, output at any given point of time depend only on the input at that time and no relationship with the past inputs. Same thing I can say in different way.
  • Circuit respond to the input without any delay (so that even if you apply any other input, it will not effect the output correspond to previous input)
  • The time interval between the two successive inputs are so long that within that time circuit respond to the first input.(Means when you apply second input, output is already generated correspond to first input).

but there are situations when an output depends on the present input and condition of the circuit at that time ,which is because of previous input/inputs. This (condition of circuit because of previous inputs) is consider as "storing" the information (means there is a "Memory element") correspond to past inputs.

Note : Basic difference between the Sequential circuits and Combinational Circuits are already explained in the Topic "Combinational Circuits".

Now from definition point of view we can say that
" A digital Circuit is a sequential circuit if it's outputs at any given time are function the external inputs at that time and sequence of past inputs. "

On the basis of tis definition we can classify sequential logic into two models.
  • Mealy Model
  • Moore Model

From the above figure, you can see that there are 2 types of Inputs
  • Primary Inputs from External World
  • Secondary Inputs which describe the condition of circuit at the arrival of present inputs.

On the basis of Output from the Combinational Circuit, these two models (Mealy and Moore) are classified.

In Mealy Model - External Outputs depend both on inputs from outside world and on the feedback inputs from memory.

In Moore Model - Output does not depend directly on external inputs. External Inputs causes changes in memory, after which external output emitted from the memory.

In both the above model two thing are hidden which may be or may not be figured out by you.
  1. Expected output correspond to every Input
  2. "Stability of circuit".
Expected Output correspond to every Input
When ever you apply a input to a circuit, you always expect certain output. Even in above models (Mealy and Moore), when ever you apply a input you know the state of the circuit (condition of the circuit because of the pervious inputs), so it's easy for you to predict the output after certain time (because you have designed that circuit). In case, we don't get expected output, we start tracking back the reason of that.

Stability Of Circuit:
You have applied 1 input which will make some changes in the state of the combinational unit, which is then make changes in the Memory unit (so called feedback unit). Output of the memory unit, which is again feed back as input to the combinational circuit changes the state of the combinational circuit. This process goes on till the time circuit become stable.

From the time of the initial change in input and the final change in output takes place there is a period of instability. If a further change in primary input takes place during this period of instability. the circuit might fail to give a expected output because it isn't clear what the contents of memory are when second input applies. There are changes of the Glitch.

Lets assume that you provide a input to a circuit and you are expecting some output, but before output settles to your expected value, there is/are some unwanted transitions (one or more). And these Transitions are known as Glitches.

There is only one good solution of this problem. Disconnect the whole system (circuit) from the external world till the time it become stable. Once It become stable, reconnect it. This Disconnect and reconnect usually done with the help of an extra signal, commonly known as Clock (some time Terminology "Enable Signal" also works).

We will discuss about the clock in some other Article. This Article is not for Clock. :)

Now we can say that there are 2 Types of Sequential Circuit
  1. Non-Clocked Sequential Circuit
  2. Clocked Sequential Circuit

In a Design there may be several clocked sequential circuits interconnected which have different Enable signal (Connect and Reconnect Signal from the External World - Clock Signal). Means One circuit is clocked by CLK1 and other is CLK2 are interconnected. If that's the case, again same problem came into the picture as we have discussed above. Because one circuit don't know when other circuit become stable (or say produce a output after internal stability). So they can't be disconnect or connect as per the other circuit's output (Both circuits are not synchronize with each other). Again same case of Glitch can be there.
If both circuit can be synchronize with each other, this problem solved. And this can be done with a common Clock signal. :) So I can say from Definition point of view that
"If all the enabling clocks in Interconnected circuits are the same, then activity in all circuits will occur synchronously. Such Circuits are known as Synchronous Sequential Circuits".

That Means above category can be renamed as (which is more common)
  1. Synchronous Sequential Circuits ( Clocked Sequential Circuit)
  2. Asynchronous Sequential Circuits ( Non-Clocked Sequential Circuit)
Note: Difference about these 2 type of circuit already discussed in the Article "Combinational Circuits"

In the next Article, we will discuss more about the Synchronous Sequential Circuits.

Tuesday, November 17, 2015

Low Power: Introduction

Introduction: "Why Low Power is in Demand in Semiconductor Field"

This series consists of several Article related to Low power concepts. You might be thinking that why this series because already a lot of material is present over the Net about this. And my simple Answer of this – I want to discuss all these details once again on the basis of my experience. I will try to present it in simpler language / Style which can help you to understand the concepts. I came across several articles which require some basic understanding at least. But here I will try to capture the things in such a way that anyone can understand low power concepts.
I can only try – let’s see how much I can get success. 

Very first question is why “Power is such a Big concern and need a solution”? Why everyone is talking about power and especially Low power.
Before I will explain this in more technical way, let me try it in layman language. All of us use cell phone and as the complexity/feature of the phone increases, battery backup decreases. In the market everyone is trying to get more battery backup without compromising with the Features of Cell phone. How it can be possible? Only one way is to reduce the battery consumption (power consumption) of the cell phone. Or I can say that cell phone should start functioning (in the similar fashion as before) in less power (low power consumption). That’s the reason everyone is talking about low power.
In the Semiconductor Industry, It’s a big concern. On the top of this the size of chip decrease day by day and so Power consumption is getting more and more importance. You may be thinking that if you decrease the size of the device, power consumption should also decrease. But unfortunately Power consumption is not directly proportional to size of the chip. (I will explain this in more detail later).

For higher technology nodes (may be higher than 320um), main parameters of concern were:
  • Timing
  • Area.

In the lower nodes, even after reducing supply voltages, threshold voltages (which reduce the power consumption drastically) power consumption is not in the same proportion as we were expecting. This is all because of several factors. One best example is Leakage current. The device (transistor) densities and clock frequencies also increases for lower nodes which increases power consumption. So in short there are several ways which helps to reduce the power consumption but on other side there are several factors which increase the power consumptions.
In this series, we will discuss all these things in detail.
Right now it’s very important for you to understand that power consumption levels have reached their acceptable limits (now a days) and that’s the reason power has become as important as timing or area.
So now we have 3 main parameters of concern:
  • Timing
  • Area
  • Power

(Note: In this series, we will discuss only about 3rd component - Power :).

Below are few points which will further help you to understand why now a day’s power consumption increases and why it’s important to discuss low power solutions. (These are just few points but in actual there are lots).
  • Shrinking feature Size (You might be thinking that for smaller gate the power consumption should be less then how this can be cause of high power.)
    • Gate densities have grown faster than scaling theory predicts.
      • Number of metal layers increased too
      • Wiring and gates are not scaled equally
      • Gates are not scaled equally in all dimensions
    • So overall consumption of Power increases.
    • Leakage power increases as feature sixe decreases.
  • Faster processing speeds
    • More switch On – Switch Off
    • More charging and discharging.
    • More power consumption.
  • More functionality
    • More power requirement.
  • Implementation of analog functions in digital
    • high speed, high complexity DSP
    • continuous data
  • High Die temperature
    • If power dissipation is not proper, temperature of gate/device increase
    • Lots of characteristic (like ON current) are temperature dependent. So hotter the area, more chances of fail of a chip in that area (if not taken care while designing).
    • For chip to work, output drivers need to be over-specified/characterized to guarantee drive at maximum ambient temp
    • This means increased power dissipation at all temps
  • High Power consumption increases (because of any of the above reason)
    • The temperature of the chip.
    • Sufficient heat sinks and cooling system is required which are expensive and some time bigger than the devices.
    • Reduces the battery Life. So require the bigger battery or powerful batteries which are expensive and again bigger in size.
    • Low-cost products must use natural convection or conductive cooling
  • Low cost packaging

Now, you should have a fair idea why reduction of power consumption is required and why every where you are listening LOW POWER – LOW POWER.

There are lots of methods and areas which are recommended or researched for low power design. Like

From Design Methodology point of view:
  • Use of UPF/CPF so that you can take care of power as early as possible.
  • Use of several special types of cells which can help you to reduce power (Like Isolation cell, retention cell).
  • Libraries are characterized based on Threshold voltages (High Vt , Low Vt) so that it can be used as per the requirement.
  • Different techniques to isolate a portion of design (if not in use).
  • Divide the design as per the power requirement (Multi Voltage domain).
  • Stop clocking a device/portion of design (if not in use)
    • Note: it’s different from “Not providing Power” Vs “Not providing Clock”.

From Physics Point of view:
  • From BJT to CMOS
  • Planar FET (CMOS) to FinFet
  • Reduction of Power Supply
  • Frequency scaling
  • Variable Threshold CMOS (VTCMOS)
  • Experimenting with the Doping level /concentration
  • Experimenting with the several type of Capacitance.

From Chemistry point of view:
  • Use of different Metal so that Resistivity decreases (reduce power dissipation)
    • Like Cu Vs Al
  • Different type of Dielectric (HighK , LowK)
  • Experimenting with the Gate Oxide

We will discuss all these in detail from Power point of view in next coming Articles.

Thursday, October 29, 2015

Metal Width Variation (Summary)

Summary of Metal Width Variation

Now, I think this much is sufficient for the width variation. Let’s revise few of them.

Below figure has
  • Ideal shape (which we draw on layout or say theoretical shape)
  • Practical Shape (Which will come after different manufacturing variation effect).
    • Here, I have flipped the shape of “practical shape” which we have discussed till now to show you that if you understand this then you can model any type of shape.

Below figure explain about the modeling as per variation Type2:
  • Red color dotted shape is Ideal shape / Layout shape or say Theoretical Shape.
  • Light brown color shape is Desired Shape.
  • Green color shape is modeled shape (as per variation type 2)
  • In variation type 2, top and bottom delta are same.
  • Since modeling is with respect to theoretical shape’s edges, it’s difficult to model exact delta either on Top side or bottom side. But this one is more closure to the desired shape.

Below figure explain about the modeling as per variation Type3:
  • Red color dotted shape is Ideal shape / Layout shape or say Theoretical Shape.
  • Light brown color shape is Desired Shape.
  • Green color shape is modeled shape (as per variation type 3)
  • In variation type 3, top and bottom delta can be different and that’s the reason we are able to match top and bottom delta width properly (except right hand side bottom delta).
  • This is because Variation type 3 has condition that
    • top width delta on either side should be same
    • Bottom width delta on either side should be same.

Below figure explain about the modeling as per variation Type4 along with the variation Type3:
  • Red color dotted shape is Ideal shape / Layout shape or say Theoretical Shape.
  • Light brown color shape is Desired Shape.
  • Green color shape is modeled shape (as per variation Type3 and Type4)
  • In variation type 3, top and bottom delta can be different and that’s the reason we are able to match top and bottom delta width properly and in type 4 right and left side variation can be different and that the reason we are able to match right hand side bottom delta (which were missing in the type 3).

In the above figure related to non-linear top-to-bottom variation can be modeled with the help of Variation type 5.

Below figure explain about the modeling as per variation Type6 (basically it will explain now from the Top view – which also include the length of the metal wire)
  • Red color dotted shape is Desired Shape (which will come after manufacturing). (Note: here just changed the color scheme)
  • Light green shapes are as per modeling (after applying variation type6)
  • Dark green (in reference to above point) shapes are Ideal shape / Layout shape or say Theoretical Shape.

For variation type 7 below figure is self-explanatory. I think it’s not required to give much more details of that. Just remember that these 2 wires are oriented differently (one in vertical and other in horizontal).

For variation type 8 again below figure is self-explanatory. Just point to noted that it is because of n number of non-uniformities. It effects differently for Resistance and Capacitance. This variation type can be combined to any other variation type and accordingly can be modeled.

Tuesday, October 20, 2015

Metal Width Variation (Type 8)

Metal Width Variation (Part 6)

Width Variation Type 8:

There are few data provided by the foundry which is only effecting the Resistance or Capacitance of the design. Means there are different width variation values for effecting the Resistance and Capacitance. These type of info usually provided by 2 different tables (for any type of the variation), one specific to Resistance and other specific to Capacitance.
I know you might be thinking that how it can be possible.

Before I will explain that, it’s my duty :) wanted to remind you following thing. In design wire is long and thick (like showed in the 3D view). Length part which I am referring to is 2D view (Top View in below picture) and Thick part which I am referring to is 2D view (Front view in below picture).

In previous articles (where I have discussed about the different type of Width Variations), I have explained the width variation Type 1 to 5 using the Front-View and Variation type 6 -7 using the Top View.
Actually, in design it’s the combination of both views.

Everywhere, we are talking about the variation linearly But what about the below picture?

Yes, now we are talking about the non-uniformity in the wire itself. These non-uniformities can be introduced as part of Etching, Deposition or Lithography process. And remember, these are different from what we have discussed till now (Means variation type).

Now, if I will ask you how to model these non-uniformities, then maybe you can say that it’s very simple. Let’s take the average of this and model it as part of Width variation type. Means the calculation of the values of Bias which we are going to apply on the width should be as average value of these non-uniformities.
Your approach is 100% correct but there is catch.:0 :)You have mentioned “Average of these non-uniformities”, that’s the part I want to stress here … Average of non-uniformities in terms of which parameter? These non-uniformities have different effect on Resistance and Capacitance calculation. How? :) :)

C is more determined by outer edge of interconnect, R by average resistivity.

In case of C, when I am talking about the outer edge,
  • These non-uniformities can change the distance between 2 adjacent metal wires at different point (along the length of wire), so while you are averaging the effect – may be you will consider this factor and then come up with an average biasing value which suppose to apply on width of wire.
  • C is related to deposition of Charge in a plate (outer edge of plate) (we have studied this in school. There will be a lot of irregularity or say non-uniformities in the density of charge at each and every point of layer (sharp edges Vs flat edge) and if that’s the case – we have to consider that part also while doing averaging and decide a final bias value for entire edge.

In case of R
  • We are more concerned about the flow of current (Means flow of electron). So mobility, drift current, effective current – these concepts comes into the picture. So while averaging these non-uniformities for R, we will consider these factor more in compare to outer distance from other metal.

You can now imagine that the same non-uniformities effects Resistance and Capacitance differently and if we want to model this – we have to divide our variation into 2 categories.
  1. Width variation for Resistance.
  2. Width variation for Capacitance.

Now let’s talk about one more reason of this. :) Below picture is self-explanatory (I think so). Color shades represents the metal density.

Now, may be you are thinking, why it will happen and how it will effect Resistance and Capacitance.

As, we have already discussed that interconnects are fabricated using 2 major steps
  • Etching a portion of dielectric and
  • then fill it up with the interconnect material.

This filling is done in different steps and somehow final material does not have uniform resistivity in cross-section (horizontal or vertical). Just because of this we have to apply different biases for R and C as a function of width.

Etching is done by bombarding loaded particles out of a plasma on the wafer surface under guidance of an electrical field. This field is not uniform but is (slightly) deformed by longer range density of the pattern and influencing etch speed. Additionally the etched away material may also influence local etching performance.

Variation info can be in the following way.
Note: I just took the example from variation type 1, but same concepts can be applied for other tables or other type of variation parameter also.

Table 10: Different Bias Value for Resistance and Capacitance effect
Metal Layer Width (um) Variation in % (+/-)(Resistive Only) Variation in % (+/-)(Capacitive Only)
Metal 1 0.2 8 9
Metal 2 0.4 8 9
Metal 3 0.4 9 10
Metal 4 0.4 10 11

Friday, October 16, 2015

Metal Width Variation (Type 7)

Metal Width Variation (Part 5)

Width Variation Type 7:

Now what?? What is remaining now?:) :)Anyways – still few things are remaining. Have we discussed anything about the wire orientation? Wire width variation based on wire orientation.
Please refer the below figure and think how can you model such scenario.

Don’t think that I am creating variation type unnecessary :) it’s the scenario for lower nodes (like 28nm and below). Soon you will get the all the explanation of this. But right now, modeling is important.:). So what’s the solution? Yes you are thinking in the right direction that we will add one more parameter “Direction” along with the normal wire variation parameter. So as per you, Horizontal and Vertical are 2 different direction and we can specify 2 different biasing tables for these. But I would like to generalize this.

Usually, foundry provides the info with respect to the some reference orientation. Actually this direction concept come from the manufacturing instrument (just explained in layman language). Every machine has different accuracy margin between left-right (horizontal) and top-bottom (vertical). So orientation thing comes into the picture.

Your deign will have structure only in 2 direction (45degree structure or any other degree orientated structure are now obsolete in lower nodes) and once you decide that your reference direction (may be based on maximum structure in a particular direction or with respect to any other reason), you will apply those rules. Once your reference direction is decided, machine will be orientated for that direction.

Structure in that direction will have rules corresponding to that and for other structure (which are in other orientation) machine will behave differently (so different rules). So this reference direction is important.

Foundry will provide the rules as per Reference direction.
  • Parallel_to_Reference
  • Perpendicular_to_Reference
Variation info can be in the following way.

Note: I just took the example from variation type 1, but same concepts can be applied for other tables or other type of variation parameter also.

Table 9: In the form of absolute variation number
Metal Layer Width (um) Variation in % (+/-)(Parallel_to_Reference) Variation in % (+/-)(Perpendicular_to_Reference)
Metal 1 0.2 8 9
Metal 2 0.4 8 9
Metal 3 0.4 9 10
Metal 4 0.4 10 11

Tuesday, October 13, 2015

Metal Width Variation (Type 6)

Metal Width Variation (Part 4)

Width Variation Type 6:

After the previous variation type (especially Type4), where I made a sentence that “width variation also depends on the surrounding environment (like metal density or say space with respect to neighboring metal layer)”, you may have a lot of questions or questions came in your mind. Like what will happen in the below scenario.

I am sure you can say that as per the diagram and as per foundry data, small segments of wire (enclosed by dotted red box) see a very large spacing in the horizontal direction. However the next section (enclosed by dotted green box) of the same wire shows a much closure spacing. As per the modeling (whatever we have discussed till now), if large and small spacing concept are used, width (silicon width) changes drastically which we know very well that it’s practically impossible.
What does it mean???
It means … Our list of variation type is not complete. :)

Practically, the above structure will be in somewhere like below shapes after manufacturing. You can notice that the place where spacing is drastically change (Common boundary of red and green dotted box), manufactured shape is not drastically changed. There is a curve/slope or say gradient in the width variation from low value to high value.
Since our goal is to model the variation as close as possible, foundry provide these info also. So that EDA vendors can model such portion also (which can impact RES and CAP values – especially in lower technology nodes).

Info will be somewhere in the following form.

W = width of the wire,
S =space between 2 wires,
L = minimum parallel distance between 2 wires,
dD = delta distance after L length.
dW = Delta width variation = X

data/info will be as per following function
dW(W, S, L, dD) = X ;

dW(0.5, 0.5, 0.5, 0.0) = 0.01 ;
dW(0.5, 0.5, 0.5, 0.05) = 0.02 ;
dW(0.5, 0.5, 0.5, 0.1) = 0.03 ;
dW(0.5, 1.0, 1.0, 0.0) = 0.04 ;

Again this type of info can be provided in “n” no of ways and I can’t discuss all those (because that may create an issue from confidential point of view). I have just provided the concepts here which can help you to understand. If you have worked on such cases anyhow, you can easily correlate and if you haven’t (till now), then such concept is sufficient for you.:)

After modeling as per variation type 6, above wire structures will be converted into following structures (which is very closure to the actual one).

Friday, October 9, 2015

Metal Width Variation (Type 4 and Type 5)

Metal Width Variation (Part 3)

Width Variation Type 4:

Variation type 3 has condition that
  • Top width delta on either side should be same
  • Bottom width delta on either side should be same.

I know you can say that it’s easy and let’s divide the modeling parameter top and bottom into left and right side. Like bottom_left, bottom_right, top_right and top_left. But it’s not as easy as you are thinking. Because these modeling has some background. We have to think, what are different reasons which can output different left and right delta? Even I am trying to figure out the exact reason of that (if you find, please let me know ). Point is, I will update you later but till then you have to search out. 

Just a hint that width variation also depends on the surrounding environment (like metal density or say space with respect to neighboring metal layer). So in this variation type, we have to consider the fact that width variation also depends on the space with respect to neighboring metal wire. In such case foundry provide below type of info.

Table 7: Metal effective Silicon Width based on Drawn Width and Spacing pattern
Metal Drawn Width (um) Drawn Space (um) Silicon Width (um)
Metal 1 0.5 0.5 0.409
Metal 1 0.5 0.75 0.429
Metal 1 0.5 1.0 0.439
Metal 1 0.5 1.5 0.448
Metal 1 0.75 0.5 0.682
Metal 1 0.75 0.75 0.701
Metal 1 1.0 0.5 0.930
Metal 1 1.0 1.0 0.960
Metal 1 1.0 1.5 0.969
Metal 1 1.5 0.5 1.420
Metal 1 1.5 1.0 1.449
Metal 1 1.5 1.5 1.459

Similar type of table you can get for other metal layers with more spacing and width points. These are just for the reference level. Also remember – in place of Silicon Width, info can be in the form of delta value or delta %. It depends on foundry to foundry. 

Sometime same info can be provided into following way (final silicon width with respect to different drawn width and spacing combination)

Table 8: Metal effective Silicon Width based on Drawn Width and Spacing pattern
w/s 0.1000 0.1300 0.1500 0.2000 ...
0.1000 0.1025 0.1125 0.1220 0.1470 ...
0.1300 0.1265 0.1285 0.13400.1525 ...
0.1500 0.1459 0.1459 0.14590.1599 ...
0.2000 0.1783 0.1783 0.17830.1783 ...
... ... ... ... ... ...

You may ask now, how it will remove the constraint of Type 3 variation. Very simple… left and right side variation in width can be figure out as per the environment around a particular metal layer. Please refer below figure for more understanding. It will help you to understand how left and right variation can be coded differently without using “left” and “right” keywords.

With the help of combination of different type of variation we can model anything. Like different top and bottom delta (using Type variation 3), different left and right delta (using type variation 4). As I have described in type3 how to combine different variation types, same process we can use along with Type 4 and come more closure to actual silicon structure.

Note: In above figure X1, X2, X3 and X4 can be equal or may be different.
Using the variation type 4 (along with other variation type), we are more closure toward the actual shapes after the manufacturing. Please refer the below comparison. (Note: here bottom_delta and top_delta are different along with right and left bottom variation also).

Width Variation Type 5:

Question is what’s now missing. There is one point which we are assuming continuously that variation will be linear in shape from top to bottom but in actual that’s not the case. Like in the below figure.

What’s the solution of that! Very simple – provide the equation or “order of polynomial equation” of variation from top to bottom. 
Fortunately, till now I didn’t come up with any such data provided by Foundry. May be it’s not that important till now or Foundry don’t want to make modeling so complex.(Good for EDA vendor). But this is a proposed solution from me for future. 

Reference: "Including Pattern-Dependent Effects in Electromagnetic Simulations of On-Chip Passive Components" by Sharad Kapur, David Long, Tsun-Lai Hsu, Sean Chen, Chewn-Pu Jou, Sally Liu, Gwan-Sin Chang, Cheng-Hung Yeh, and Hui-Ting Yang (Download)

Tuesday, October 6, 2015

Metal Width Variation (Type 3)

Metal Width Variation (Part 2)

Width Variation Type 3:

In this, we are just removing the restriction which we have imposed in the Type 2 . Means in this

“Bottom delta” ≠ “top delta” (top_width_delta is_not_equal_to bottom_width_delta)
Concept wise everything else remains (as in the width variation Type 2) same but just provided info will be little bit different.

Table 6: In the form of absolute variation number
Metal Width (um) Top_delta/bottom_delta
Metal 1 0.2 +0.01/-0.02
Metal 2 0.4 +0.01/-0.02
Metal 3 0.4 +0.01/-0.02
Metal 4 0.4 +0.01/-0.02

Here I have used different value for Bottom and Top Delta.
Note: Similarly we can have other tables also (similar to table 2 and 4).

Structure wise after applying the variation type 3, we may get below patterns or we can say that we are modeling only below type of variation in the shapes.

Now a simple question…
Can you model this type of variation (Type 3) using tangent values (tan Ɵ) as we have done in the last post (table 5)?
I know, instantly – you can say yes. But remember in case of “tangent”, variation from the vertical line either on top or bottom should be same. Means as shown in figure.

So, now how can you model this type of variation? I am sure something may be clicked in your mind. What about shifting the vertical line little bit outside the actual shape edge. Means, what about applying variation Type 1 first and then variation Type 2.

(Note: Color of original shape changes because of overlapping of other shapes – so please dnt mind or say confused by the color)

We have applied Type 1 variation (discussed in previous post) on the very first shape (Edges AD and BC). New shape is with edges “ad” and “bc”. On this new shape, apply Type 2 variation with some angle (or may be same top and bottom delta width value). This will give you a new shape (trapezoidal) with edges UV and WY.
In the following diagram, you can see that original shape (Ideal one) is in blue color and Final shape (practical one – after variation) is brown in color. Here X1 is not equal to X2 (means top_width_delta is_not_equal_to bottom_width_delta).

This method also shows you the importance of Variation type1 (for those who may be thinking that variation type 1 is not a practical one, so what’s the important –I hope, they should know the importance of that.)

Using the variation type 3, we are more closure toward the actual shapes after the manufacturing. Please refer the below comparison. (Note: here bottom_delta and top_delta are different).

Now, first one are 99% matching (except few curves on the edges) but 2nd figure still have some mismatch. Variation type 4 can help in that.

Sunday, October 4, 2015

Metal Width Variation (Type 1 and Type 2)

Metal Width Variation (Part 1)

In the previous articles, we have discussed a lot about the Etching, CMP, Lithography and their effects. Now it’s the time to know
  1. How these variations are modeled in real?
  2. How foundry provide the corresponding data?
  3. How to read that one and provide the info to different tools?

Let’s start with the Summary figures of last post.

Note: Blue is what we need ideally and brown is what we will get actually/practically.

As we have discussed in last few post that there are basically 3 parameters which are affected a lot.
  • Width of metal
  • Thickness of Dielectric and
  • Thickness of Metal.

From the above figure and also from statement, you can easily conclude that there are 2 mainly type of variation – In width and In height. Let’s start one by one.

Width Of Metal:

There are different ways to model variation information of this parameter. Different EDA vendors code this info in different way (I will summarize this in the last of this Article series). Similarly, Foundries also provide this info in different way.

Width Variation Type 1:

Most common and simpler form of variation is “variation in percentage” or “absolute numbers” in the form of table.

Table 1: In the form of variation %
Metal Width (um) variation in % (+/-)
Metal 1 0.02 8
Metal 2 0.04 8
Metal 3 0.04 9
Metal 4 0.04 10

Structure wise after applying the variation type 1, we may get below patterns or we can say that we are modeling only below type of variation in the shapes.

In this type of variation, we assume that width variation is same from top to bottom OR if there is any difference, their effect in Capacitance and Resistance are negligible. I have just used 2 words, CAPACITANCE and RESISTANCE, so it’s my moral duty to ask this question- “How, above type of width variation impact the CAP and RES of the Circuit?” :)

I would say – think and if you forget then please refer Parasitic Interconnect Corner article. It will help you to refresh your concept And don’t worry I will also summarize this later on.

Width Variation Type 2:

In this we will remove the restriction of Type 1 (same bottom and top width variation). It’s now more closure toward the practical shape. And foundry consider this for 180nm and below nodes.

Ideal Width of Metal = W (Rectangle shape)
Because of several fabrication steps (already discussed in last few Articles of this series), final shape of the Metal is not rectangular. It’s trapezoidal, so we have to define 2 widths.

Top_width = W+2A
Bottom_Width = W-2A


  • Here we are considering that “bottom delta” = “top delta”.
  • In case, top_width_delta=bottom_width_delta, we can model this by using the angle Ɵ also. Where tan Ɵ = 2B/2A and known as Tangent.

So, in all the above case the table (or say info provided by Foundry) can be any of the following.

Table 2: In the form of absolute Numbers (final width)
Metal Width (um) Top_width/bottom_width
Metal 1 0.2 0.21/0.19
Metal 2 0.4 0.41/0.39
Metal 3 0.4 0.41/0.39
Metal 4 0.4 0.41/0.39

Table 3: In the form of absolute variation number
Metal Width (um) Top_delta/bottom_delta
Metal 1 0.2 +0.01/-0.01
Metal 2 0.4 +0.01/-0.01
Metal 3 0.4 +0.01/-0.01
Metal 4 0.4 +0.01/-0.01

Table 4: In the form of % delta variation number
Metal Width (um) %Top_delta/%bottom_delta
Metal 1 0.2 +5%/-5%
Metal 2 0.4 +10.0%/-10.0%
Metal 3 0.4 +10.0%/-10.0%
Metal 4 0.4 +10.0%/-10.0%

Table 5: In the form of Tangent (angle)
Metal Width (um) Thickness (A) tan Ɵ
Metal 1 0.2 1000 5
Metal 2 0.4 1200 6
Metal 3 0.4 1200 6
Metal 4 0.4 1200 6

Structure wise after applying the variation type 2, we may get below patterns or we can say that we are modeling only below type of variation in the shapes.

I am sure you are able to co-relate these with the real structure or shapes (Snapshot of last few article summary). But if you are still confused, please refer below figure.

After seeing above figure, you may be thinking that it’s not 100% matching. For that variation Type 3 can help you.

Thursday, September 24, 2015

Design Exchange Format (DEF)

Introduction to Design Exchange Format (DEF)

Design Exchange Format (DEF) . is used to represent the physical layout of an IC in an ASCII format. It represents the netlist and circuit layout. We used DEF along with LEF (Library Exchange Format) to represent complete physical layout of an integrated circuit while it is being designed.

Origin : DEF was developed by Cadence Design Systems.

Generated by : Usually generated by place and route (P&R) tools and are used as an input for post analysis tools, such as extraction tools or power analysis tools.

Now here I am not going to describe the different syntax used in the DEF, But I will concentrate on what exactly DEF is!
Actually DEF is a text file which you can read and easily figure out the different information about the layout. like
  • What are different components in your design ?
  • Where these components are placed in you DIE ?
  • How these components are places ?
  • What's the size of the DIE ?
In Semiconductor terminology, it will tell you the
  • Macros of design
  • Placement information
  • Pin locations
  • Metal blockages
  • Orientation
Now let me explain this with the help of 1 example of you house. You have to draw a picture as per my description mentioned below.
  • You have a plot of 100x100 meter
  • You have to keep a margin of 2m at all the four side. Margin - Open area, no construction should be done in that area.
  • From coordinates (2,2) to (10,10) - it's a 8x8 meter Kitchen area
  • There are 2 doors of 7ft in height from 10,5 to 10,6 and 2,10 to 3,10.
  • One T shape Hall (along with a small pathway) is present which has following coordinates. (10,2) (10,10) (2,10) (2,14) (10,14) (10,40) (40,40) (40,2)
  • One master Room is present with coordinates (2,14) (10,60)
  • One attached balcony with the Master Room with coordinates (2,60) (10,80).
  • From (10,40) (50,80) another Room
  • Attached bathroom (50,40) (60,80)
  • (40,40)(60,20) is used for Stairs
  • These Stairs will go till 3rd Floor, so no other construction on top of this place
  • (40,20) (60,2) - third room
Now If I will provide you this much of info, you can easily come up with a Layout. 
Similarly, we can define the Door location / Window Location, Electricity fitting, Pipe line and all. Lets try to correlate the same with the VLSI terminology and then you can easily figure out what all are present in the DEF.

Plot size >> Core Size / Die Size
Rooms and Kitchen >> Macro placement
Kitchen / Bedroom / Bathroom >> Different Blocks with some characteristic. Which we also define in DEF.
Window/Door Location >> Pin placement
Passage >> Routing Information
Floors >> Metal layer Stack
Open Space info >> Related to Blockage information.
Entrance to House >> Pin location which Interact with outside world.

There are few more info which you can define as Part of DEF.
  • Specifies that the component has a location and cannot be moved by automatic tools, but can be moved using interactive commands.
  • For specifying the Hierarchy name, which Divider Character you want to use "." or "/" can be defined in DEF.
  • Metal Fill Details
  • Units for different type of Dimension related info
  • Defines any Non Default Rules (NDR) used in this design that are not specified in the LEF file.
  • Pin related info. Like
    • Which type of Pin it is ?
    • Pin connection (in case it's connected to Ground or Power VSS/VDD)
    • It's a power pin or Signal Pin or Clock Pin or SET/Reset pin etc
    • Pin orientation
  • Rows, Sites, Tracks
    • Placement of Standard Cells are done by the tool (Automated Process).
    • Think the difference when I will ask you to arrange 100 things in a Big Box Vs In a Almeria which have drawers. In Box - you can put all the stuff but that will not be so organized as it will be in Drawers.
    • In the drawers, you have to follow certain rules (size of Drawers and spacing between Drawers).
    • There may be more space available in Box but it's difficult to reach those Items very easily randomly
    • Similarly, in Design we come up the concept of Rows, Sites, Tracks.
    • During the placement it's easy for Tool to place different standard cells or macros with in these Rows / Sites.
    • Tracks helps during Routing.
    • You can correlate these with the Foundation and Pillars during Home construction which provide a frame for placing the Bricks between them.

You will get the layout information above Metal1 in the DEF. It will not contain any info about the Diffusion or Poly or any other layer which are below Metal1. And that the reason it's Used in Digital Design. Means when we are talking about LEF/DEF flow - means we are talking about Digital Flow.

Now there are few things which you will not define as part of House layout because that info you will get somewhere else. Sink / Taps / Electric fittings, Size and shape are predefined. So you don't have much control. You can choose which one you want to use but you will not prefer to manufacture those one. You can consider these are like Standard Cells, which are already defined and designed by someone else. You have to just place those things. Whatever minimum information you require during you Designing the layout, that info you can get through Standard Cell LEF. We will discuss about LEF in Next Article.

I think, I have tried to cover each and every thing which should be part of DEF. Now just Syntax is remaining. Few of them are:

[ VERSION statement ]
[ DIVIDERCHAR statement ]
[ BUSBITCHARS statement ]
DESIGN statement
[ TECHNOLOGY statement ]
[ UNITS statement ]
[ HISTORY statement ] ...
[ DIEAREA statement ]
[ ROWS statement ] ...
[ TRACKS statement ] ...
[ GCELLGRID statement ] ...
[ VIAS statement ]
[ STYLES statement ]
[ REGIONS statement ]
[ COMPONENTS section ]
[ PINS section ]
[ BLOCKAGES section ]
[ SLOTS section ]
[ FILLS section ]
[ SPECIALNETS section ]
[ NETS section ]
[ SCANCHAINS section ]
[ GROUPS section ]
[ BEGINEXT section ] ...
END DESIGN statement

You can get more detail about the Syntax and their Description from the Below Document:

Wednesday, September 23, 2015

Blockage: Placement and Routing In design

Blockage In Design

There are 2 type of Blockage from definition point of view.
  1. Placement
  2. Routing

Blockage can be Area specific or can be Component Specific (associated with Instance). If it's associated with any Instance - Means - the moment you move Instance from one location to other (with in the Chip), Blockage also move along with that.

You can also associate the type of components which you want to block. like
  • Standard Cell
    • If you are saying that you have applied Standard Cell Blockage in a area, Means you don't want tool place Standard Cell in that certain area. And that's the reason such Blockage we termed as "Standard Cell Blockage"
    • Question is: What is the need of this?
      • There are some areas which we want to reserve for Routing purpose and that's the reason we don't want to put standard cells there. Usually we do this to reduce the congestion in a particular area.
      • Some time we are okay with the inverter and buffer in certain area but don't want to put any other Standard Cell Blockage. Like between 2 Adjacent Macros. In this area there is a narrow channel and if we will put standard cell then it can create a Congestion, so avoid placing standard Cell. But in that area there are pins of macros and there may be requirement that you need to put buffers or inverter before those pins (to increase the drive strength or improve transition time or invert the logic). So you have to allow these 2 type of Standard Cells. These are termed as "Non-Buffer Blockage".
  • Macros (Halo) blockage : usually placed around Macros so that no other macro sit adjacent to that (To save routing congestion at later stage)

In case of Routing Blockage, you have to define Layer Number which you want to block. I means to say, there is a area X and In that area you don't want any net to be routed using the Layer M1,M2,M3 but you are okay with M4 passes over that area. Such type of Blockage comes into the category of Routing Blockage.

Similarly, you can also Block a reason for a particular type of Net (on basis of Net property). Like you want to block a Signal Net but there is no issue with the Power Net. In that case, any signal nets on any layer will not cross that area but Power Net can be easily routed in that area.

You can ask what's the reason of doing this. Why we don't want to route a particular type of Net or Particular Metal layer over a certain region.

Simple Ans is:
Suppose you have a Block/Macro which is noise sensitive and you want to prevent any signal routing on specific layers above the block Because signal has a nature to change or fluctuate, which can introduce Noise in that block. Based on the Sensitivity factor toward the Noise and Noise margin you can decide whether you have to block all the layers of some specific layers.

Suppose topmost routed layer inside Block/Macro is M2 and block is sensitive up to 2 level of Metal layers (M3 and M4), then you can block only these 2 metal layers and allow other metal layer routed on the top of such Macros/Blocks.

But in case it's very-very sensitive with any change in the signal in any layer and also Noise margin is very less, then you can block all the Signal Nets (on any layer). But in that case you are okay if Power rail passes over that (I am sure you know the reason :)). Power Signal may be either VSS or VDD - means "0" or "1" and don't change frequently. Even if they are changing at any point of time (when you are doing shutdown, disconnect a particular block) there should not be any issue because such things happen in the time frame which is far-far bigger then the clock frequency. E.g. After 1 hr for a Block which is working on 10GHz frequency. Means you have to block only signal Nets.

By Now, I think you are clear with the concept of Routing Blockage.

You can place the Blockage for Metal Fills. Means no Metal fill can be placed in that area. why this requirement ? Do some brainstorming.. :) :) Just few hints on which you can think.
  1. Why we do Metal fill ?
  2. How it will effect the CAP or say timing of circuit ?
  3. At which step you are doing Metal Fills?

EDA Tool also give you the Flexibility to define the percentage of Blockage. Like, In a particular area, density of standard cells should not be greater then 50%. What exactly we are doing here - We are telling tool that they can place the standard cells in this area till the time it's occupancy is less then 50%. Once that's achieve, no more standard cell is required. There are few reasons of this.
  • We are doing this early in the design, to save this place of Routing resources later on.
  • We don't want congestion. (other way to say above point)
  • We want to use this place for future optimization.
  • We want to use this place for Clock tree buffer insertion.

Other type of Blockage on the specified layer where slots cannot be placed.

In the last I want to stress on 2 points (which if you remember, will help you a lot)
  1. Blockage is a feature which Tool provides to user. Any type of Blockage can be possible if Tool allow. In case tool don't allow then you have to figure out any other way. If EDA vendor come to know that it's a good feature and help other customer also, they can implement it in their tool with a new Switch :).
  2. You can apply any Blockage at any point of time (before any particular Step of Physical Design PD) and can remove any point of time. It will help you a lot from Design perspective + methodology side

Example of #1 - I have explained later in the article.
Example of #2 - Suppose you don't want to place any Clock Net in a particular reason but okay with other Type of nets. Best thing to do it - Apply Routing Blockage during the CTS (At the time you are creating the Clock net structure) and no need of any such blockage before and after this.
Note: Scenario #2 is very common in the Industry.

Now let me capture few Questions on this Topic, which can be asked in a Interview or May be it will help you to understand this Topic more clearly. Do the Discussion with your friends and Read this article again and again if you don't figure out the Answer. :)

  1. What do you mean by Routing Blockage ?
  2. My design has 7 metal layer stack. Can I block a specific layer (not to route) on a specific area ?
  3. What about if I want to Block only M3 and M5 ? Can I do that ? What's the disadvantage of this ?
  4. Why someone want to block only "Signal Nets" and allow "Power Nets" ?
  5. In which Scenario, we also prefer To Block Power Nets (Power Ground Nets) ?
  6. When we are Applying Routing Blockage over a certain area, is it only for Global routing / Detailed Routing or for Both ?
  7. Suppose, 2 macros are communicating with each other and I don't want them to Interact using the routing resource of M3. Can I do that ? If Yes how ?
  8. Can I block VIAs also ?
  9. If I want to block only specific Nets like Critical Nets or say "Clock Network Nets" in a particular area. Can we do that ?
  10. What do you mean by the "Placement Blockage"?
  11. Can we place the blockage for Metal Fill only? If yes, Why we want to do this ? Can't this be controlled using Metal Density rules ?
  12. There are 2 type of Metal Fills (Floating and Grounded). Is it possible that I create a blockage only for Those metal fills which are grounded ?
  13. There are some special Cells, like ENDCAP CELLS , TAB CELLS, Level shifter. I want to create a blockage only for these specific Cells. Can I do that and if Yes How ?
  14. Can I create a Blockage which is specific to Scan-Chain related FF. Means no FF in a particular area which are part of Scan chain logic.
  15. Why we want to use the Macro Blockage ? What's the need of that ? In which area/scenerio we recommend to use Macro Blockage ?
  16. What do you mean by Soft and Hard Blockage ?
  17. What's the Partial Blockage? What's the advantage of this type of Blockage ?

I can think only these questions right now which can be asked or usually asked from a candidate. They can ask the definition or the reason behind that (Logic).

Above I have a "Question related to 2 macros communicating and you don't want any net on Layer Metal3." This is the perfect example where No tool provide such feature because there is no direct command to do this. But you can write a script which can do this. Like capture those pins which are communicating with each other. During Routing define the constraint that M3 will not be used for any Net which has these input-output pin combination at there extreme end. So what you have done, with the help of a script you can achieve this.

Monday, August 3, 2015

Dishing and Erosion (CMP)

CMP (Chemical Mechanical Planarization) (Part 3)

Till now we have discussed about the CMP process, Importance of CMP and problem raised by side effects (Dishing and Erosion) of CMP. But still we didn’t discuss the reason of Dishing and Erosion (what’s the root cause of these), definition of these Manufacturing defects. And how can we minimize these.

In this article, let’s focus on these points.

As usual, I have a question for you (and obviously I have to answer that).While doing CMP, we try to remove one type of layer (on which non-uniformity is present) and saying that we are doing planarization (removing one type of layer). Is this raw material (chemicals used in CMP) same either we remove Metal or Dielectric or any other Oxide?

If question is not clear, Below figure can help you to understand my question. Step 1 vs Step 4 – in both places we are doing CMP but 1 for Dielectric and other for Metal.

Chemical substance (like Slurry), pressure, velocity and other setting are dependent on Type of layer which you want “to remove”/”do planarization”. Setting and raw material used in Step1 (CMP for Dielectric layer) should be different from the Step4 (CMP for Metal layer).

Selectivity is a terminology which I am using here. I am not going to explain this from definition point of view but it’s a concept. Rest you can build anything on that. When I am saying Selectivity – I am saying that we do the CMP on selective basis (Definition of Selectivity is different from official CMP theory point of view but to explain concept here I am using the same word but in different way).

We know “for which layer” we are doing CMP, so we create the environment in such a way that it’s become easy to do the planarization of Dielectric or metal when it’s required.

In the Step 1 (while doing CMP for Dielectric), its straight forward. Just one layer and it’s easy to do planarization (No complexity as such).

In the Step 4 (while doing CMP for Metal), initially it’s very easy. It looks to us that there is no issue. But think what will happen when Metal layer reaches to the level of Dielectric. Our polishing pad usually big in size, means it will cover metal and Dielectric at the same time. The moment Pad is going to touch the Dielectric, it will try to polish it but environment is not in favor of Dielectric (it’s for Metal). Means for polishing the Dielectric, Machine (polishing pad) has to do extra effort. And this extra effort may or may not be in favor of Dielectric. Means some problem (in layman language, I can say that you are rubbing the dielectric unnecessary).

You may ask – why we will do this. The moment Metal come to the level of Dielectric, we can stop the CMP process. Yes you are right, ideally we should do that. But still there are chances that it (rotating machine) take few extra rotations before stop or we intentionally don’t want to stop at that moment (may need to polish few more time) and I am talking about that situation. Even now if you are not satisfy, then let’s talk about below scenario.

We have wafer (as in fig a) just after Metal deposition. After CMP process, we need wafer should be as per figure (b) – ideal scenario. But what happen actually ??? There may be some metal particle remain on the surface of dielectric even after removing the extra metal over the dielectric. Even the possibility may be less but we have to make sure that there should not be any particles over the surface. For that we have to do some extra polishing (may be few more rotation of polishing pad). This is known as over-polishing.

Note: This over polishing is one of the reason for Erosion and Dishing.

If you are okay with the above 2 concepts – Selectivity and Over-polishing, it will be too easy for me to explain the reasons of Erosion and Dishing during the CMP process.

I have already explained that when we are removing the Metal then all the parameters will be as per metal layer. When we do the over polishing (to make sure unwanted Metal is removed completely), then we are also doing CMP for Dielectric (but not in favorable environment). By doing this some dielectric also removed. But that will also remove some Metal (which should not be removed ideally). Refer below figure.

There are 2 type of metal wire.
  • Wide metal wire
  • Narrow metal wire with narrow Spacing.

In case of wide metal wire, overlap of polishing pad with Metal is more in comparison to narrow metal wire. From the CMP process point of view, remember one thing that polishing pad surface distorted during CMP process. For wide metal wire, pad asperity easily touches the Metal wire (copper wire) in the trench and scoops out soft Metal (Copper) between the harder dielectric.

So, during over polishing, polishing-pad can remove more Metal in case of Wide Metal wire (compare to Narrow Metal wire). This is what I have tied to explain in above diagram. Since for Dielectric it’s not a favorable environment, removal rate is less for Dielectric compare to Metal and that’s the reason you can see curve (dish type shape) in the Metal wire section. Obviously, for Wide metal this curve will be more compare to Narrow Metal wire.

This curve, non-presence of Good Metal, consider as defect or say manufacturing defect and known as Dishing.

I think now you can yourself figure out below points.
  • More dishing in case of Wide Metal
  • Less Dishing in case of Narrow Metal.
  • Dishing has dependence on the Width of the Metal.
  • Dishing has dependence on the surface of Metal in contact with the polishing pad. So if we want to minimize this, we have to reduce this overlapping or minimize this effect. For that we can do slotting in case of Wide Metal layer (If we can’t replace the wide metal layer with narrow Metal wire – it depends on design requirement).

Now lets’ take the scenario where both type of Metal wire present (Wide Metal wire and narrow Metal wire). (Blue color Metal wire)

In this case 2 concepts applies.
  • Over polishing time.
    • In case of wide spaced metal,
      • Presence of small particle outside the defined area (area of Metal wire slot) can be considered.
      • No Electrical shorting and other effect will be there.
      • Over polishing will be there but not extra or say for less amount/duration.
    • In case of narrow spaced metal
      • Presence of small particle can result to electrical shorting, can increase the cap value or may affect the circuit in some other way.
      • So we have to be extra sure or confirm that there is no particle remaining on the surface.
      • This extra surety will result extra duration of over polishing.
      • More over polishing means more removal of Dielectric layer from the design.
  • Pattern Density
    • As the pattern density increases, dimension of the Dielectric decreases.
    • The pressure on the dielectric also increases which enhances the aggressiveness of the slurry toward the dielectric and assist in mechanical abrasion.
    • These combined effects account for the dramatic increase removal of Dielectric from the surface.

Same thing I have tried to explain in the Diagram. You can see that when metal wire is closely placed, Height of the Dielectric decreases. And that effect is known as Erosion. I am not saying that “widely placed wire” don’t suffer with this effect but comparatively it’s less.

Now if the pattern density is different in different area of the chip then Erosion effect will be different as per that. In that case we can see Erosion Variation throughout the chip. To decrease the Erosion variation (within the chip), the pattern density should be uniform with in the chip. To achieve this, we do the dummy fill insertion and make sure uniform density can be maintained. Erosion increases considerably as the density of the pattern increases, regardless of the line width.

Let me summarize few of the things (which we have discussed till now).

Copper Dishing is defined as the difference in height between the center of the copper line – i.e. the lowest point of the dish – and the point where the SiO2 levels off – i.e. the highest point of the SiO2. It is caused by two factors:
  • polishing pad bends slightly into the recess to remove copper from within the recess and
  • Softer material is polished faster than the surrounding hard material.

The SiO2 Erosion is a thinning of the SiO2 layer resulting from the non-zero polish rate of SiO2 during over-polish step.
The SiO2 Erosion is defined as the difference in the SiO2 thickness before and after the polish step.

Copper dishing is strongly feature size dependent, but rather insensitive to pattern density. Oxide erosion, on the other hand, is strongly pattern density dependent, but feature size independent.

From the above discussion it is sure that over polishing is main cause of all the CMP effects. So if we can control it (Over polishing time), we can minimize these variations in the manufacturing. There are several methods – Just discussing few, so that we can understand it (as such it’s out of our scope).

CMP END Point detection: I am just discussing 2 methods in this category.
  1. Monitoring the Motor Current.
  2. Optical End Point:

Monitoring the Motor Current. When CMP process closing to end, polish pad start to contact and polish underneath layer
  • Friction force start to change
  • Current of the polish head rotary motor will change to keep constant pad rotation rate
  • Monitoring the change of motor current can find endpoint of the CMP process.
  • The moment you can figure out this peak in the motor current, you can program your machine that it shop.
  • It will help not to do the over polishing.

Optical End Point: Different material has different reflectivity (intensity of light reflected).
  • Let us suppose you are getting some intensity of light after reflection with the help of Metal.
  • You want to do planarization of Metal.
  • Keep monitoring the reflectivity and do CMP.
  • The moment it changes (because of Dielectric), you can stop the CMP process.
  • Again, it will help not to do over polishing.

Particles and Defects: Particles and defects cause irregular topography on wafer surface
  • Scattering incident light
  • Monitor particles and defects by detecting the scattered light

These particles can be detected with the help of light scattering phenomenon.

This phenomenon is used in the below method
  • Laser beam scans wafer surface vertically at one focus of elliptical mirror and a photodetector is placed at another focus
  • Moving wafer, and collecting scattered light to detect tiny particles and defects
  • Mapping particle/defect locations on the wafer surface

Reference: SIMTech Technical Report (PT/01/003/JT) “Chemical Mechanical Planarization” by “Dr Wang Zhengfeng , Dr Yin Ling , Ng Sum Huan , Teo Phaik Luan”

Monday, July 20, 2015

Importance of CMP process

CMP (Chemical Mechanical Planarization) (Part 2)

(Importance of CMP process)

Index Chapter1 Chapter2 Chapter3 Chapter4
Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Process Variation

3.1 3.2a 3.2b 3.3a 3.3b 3.3c
Introduction Effect Of Etching Process Effect Of Etching Process Introduction to CMP (Chemical Mechanical Planarization) Importance Of CMP process Dishing and Erosion (CMP effects)

In the last post we have discussed about the CMP process and very briefly raised the point of CMP side Effects (Dishing and Erosion).
Copper dishing and SiO2 erosion are undesirable because they reduce the final thickness of the copper line and leads to non-planarity of the surface resulting in complications when adding multiple levels of metal. Right now, if you are searching for definition then you have to wait. Right now I can only help you with below figure (which has some pictorial definition of these 2 effects).

You may have now 2 type of questions:
  • Why and how these issues (Erosion and Dishing) leads to non-planarity when adding multiple levels of metal.
  • Without CMP, there were also some non-planarity (I have mentioned that previously) and CMP supposed to remove that. But Now I am again talking about the Non-planarity. Then what’s the difference in both type of non-planarity.
Let me try to answer both of your questions in this Article.

First point can be understand by following figures along with their description.(Sometime Figures explain a lot compare to Description).

2D Ideal view:
Basically here I have tried to explain that if there is no issue,
  • All plates of Metal1 will start from a same reference level(or say height with respect to “0”/”zero” height of wafer). They will be coplanar.
  • Thickness of all plates of Metal1 is same.
  • Thickness of Dielectric1 should be same throughout the design.
  • All plates of Metal2 will start from a same reference level (or say height with respect to “0”/”zero” height of wafer). They will be coplanar.
  • Thickness of all plates of Metal2 is same.
  • Thickness of Dielectric2 should be same throughout the design.
  • Starting point of Dielectric2 is just above the Dielectric 1 and it will be in a straight line.

Note: You can’t see any irregularity (non-uniformity in Metal layer and Dielectric Loss) neither in Metal layers nor in Dielectric layers.

Because of CMP: 2D view:
Everything is changed. Irregularities (non-uniformity in Metal layer and Dielectric Loss) get introduced. There is a height and thickness variation.
  • Metal 1 starting level is same (because we have assumed that below that everything is ideal :).
  • Because of Dishing (Introduced as a side effect of CMP), Metal 1 thickness is changed.
  • Because of Erosion (Introduced as a side effect of CMP), Dielectric1 Thickness also changed.
    • More effected where Metal plates are present and less effected as we move away from the metal plates.
  • Since you will deposit Dielectric2 later on (After the CMP process is done for Metal1 and Dielectric1), so starting level of Dielectric2 will be as per top-level of Metal1 and Dielectric1.
    • In the below figure, you can notice that region2 was for Dielectric1 but after Dishing and Erosion, it become part of Dielectric2.
  • Now when you will deposit Metal2 on such surface, starting level of Metal2 automatically shifted (because it has dependency on the Top level of Dielectric1 (which is effected by Erosion).
  • After CMP on Metal2 and Dielectric2 structure leveling again distorted and dishing and Erosion will again take place.
  • Region4, which is originally assigned to Dielectric2 now will be part of Dielectric3.
In short I can say that:
  • Non-uniform copper and dielectric loss on M1 compounds the losses on M2 and higher metal levels.
  • CMP effects are cumulative
  • Multilevel effects impacts DOF (depth of focus), etch, and ultimately yield.

Note: These irregularity in the above figure is zoomed for your understanding but actually it’s far far better than the irregularity introduced when you will not do the CMP.  The reason I made this statement so that you don’t ask me that before and after there are irregularities, so why do CMP?  I have also explained this later.

Note: There are few recommended solution which can mitigate the effect of CMP like dummy filling and pillars/holes put in large width interconnects. I will discuss those later (this statement is going to support above Note and if same question came into your mind).

Same thing I have tried to cover into the 3D view. It may not be as accurate but you can understand what I am trying to convey.
  • Ideally:
    • Same metal thickness with certain level of leveling (from starting and ending point of view)
    • Constant Dielectric thickness and leveling across the wafer.
  • But after CMP:
    • Thickness of Metal layer changes
    • Dielectric leveling changes (Dielectric thickness Changes).
    • CMP effect Cumulates and affects other metal and Dielectric layers.

To justify my comment which I have made above that irregularity introduced by CMP is not same as before CMP, I have drawn few figure (tried my best) … (ufff few more figures).
After seeing the below figures, I am sure you can easily understand the differences and the importance of CMP. Best part is there are ways to minimize the side effect of CMP (Erosion and Dishing issue) with the help of few best practices + few other methods.

For higher nodes (like 90nm and above) these manufacturing issues are captured using the certain values based on width, spacing, density, thickness directly (also known as rule based approach via lookup tables or in the form of polynomial equations). These are present in the technology file used by extraction tool. Just an fyi that technology files are process dependent and created based on the information provided by the foundries like ICT and ITF file (We will discuss about these files later).

For lower nodes (below 90nm), due to the complexity of the process (multi-level effect) and dependency on lot of parameters (pressure, temperature, speed, pad material, slurry material etc.) it’s very difficult to exact model these variation using rule based approach.
Complexity of CMP process can be easily understandable by the following slide (captured from Internet).

Foundry and other partners develop a simulation based approach in which they take account of different effects, physical (Pad property, pressure, polish time, etc.) as well as chemical effects (slurry type, remover rate, etc.), and simulates the physical CMP process. In this approach as per the process and the design different hotspots are usually identify and accordingly corrective methods are applied. This approach is more accurate in comparison to rule based because
  • It’s not generic. It’s design dependent.
  • Different process parameters are considered and their effects are evaluated on the design. If any particular parameter can be neglected (on the basis of result), we can ignore that part also.
  • In rule based, to cover all sort of design a lot of pessimism has to be added, which can be ignored here (because it’s design dependent). It reduce pessimistic design guard band through more accurate timing/power analysis.
  • CMP model based approach also helps dummy fill optimization as compared to current rule (density) based approach (same reason as in above point – In the rule based, we have to add extra pessimism)
Note: RC Extraction can also use these “Data” for more accurate calculation of R and C. There are few Tools available in the market (like CCP – Cadence CMP Predictor, Prime-Yield).

In the next part, we will discuss about the Erosion and Dishing in detail.

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