CMP (Chemical Mechanical Planarization) (Part 3)
|Chapter 3: Manufacturing Effects and Their Modeling|
|Introduction||Effect Of Etching Process||Effect Of Etching Process||Chemical Mechanical Planarization||Importance Of CMP process||Dishing & Erosion (CMP effects)||Lithography|
|Metal Width Variation (Type:1-2)||Metal Width Variation (Type3)||Metal Width Variation (Type:4-5)||Metal Width Variation (Type6)||Metal Width Variation (Type7)||Metal Width Variation (Type8)||Metal Width Variation (Summary)|
Till now we have discussed about the CMP process, Importance of CMP and problem raised by side effects (Dishing and Erosion) of CMP. But still we didn’t discuss the reason of Dishing and Erosion (what’s the root cause of these), definition of these Manufacturing defects. And how can we minimize these.
In this article, let’s focus on these points.
As usual, I have a question for you (and obviously I have to answer that).While doing CMP, we try to remove one type of layer (on which non-uniformity is present) and saying that we are doing planarization (removing one type of layer). Is this raw material (chemicals used in CMP) same either we remove Metal or Dielectric or any other Oxide?
If question is not clear, Below figure can help you to understand my question. Step 1 vs Step 4 – in both places we are doing CMP but 1 for Dielectric and other for Metal.
Chemical substance (like Slurry), pressure, velocity and other setting are dependent on Type of layer which you want “to remove”/”do planarization”. Setting and raw material used in Step1 (CMP for Dielectric layer) should be different from the Step4 (CMP for Metal layer).
Selectivity is a terminology which I am using here. I am not going to explain this from definition point of view but it’s a concept. Rest you can build anything on that. When I am saying Selectivity – I am saying that we do the CMP on selective basis (Definition of Selectivity is different from official CMP theory point of view but to explain concept here I am using the same word but in different way).
We know “for which layer” we are doing CMP, so we create the environment in such a way that it’s become easy to do the planarization of Dielectric or metal when it’s required.
In the Step 1 (while doing CMP for Dielectric), its straight forward. Just one layer and it’s easy to do planarization (No complexity as such).
In the Step 4 (while doing CMP for Metal), initially it’s very easy. It looks to us that there is no issue. But think what will happen when Metal layer reaches to the level of Dielectric. Our polishing pad usually big in size, means it will cover metal and Dielectric at the same time. The moment Pad is going to touch the Dielectric, it will try to polish it but environment is not in favor of Dielectric (it’s for Metal). Means for polishing the Dielectric, Machine (polishing pad) has to do extra effort. And this extra effort may or may not be in favor of Dielectric. Means some problem (in layman language, I can say that you are rubbing the dielectric unnecessary).
You may ask – why we will do this. The moment Metal come to the level of Dielectric, we can stop the CMP process. Yes you are right, ideally we should do that. But still there are chances that it (rotating machine) take few extra rotations before stop or we intentionally don’t want to stop at that moment (may need to polish few more time) and I am talking about that situation. Even now if you are not satisfy, then let’s talk about below scenario.
We have wafer (as in fig a) just after Metal deposition. After CMP process, we need wafer should be as per figure (b) – ideal scenario. But what happen actually ??? There may be some metal particle remain on the surface of dielectric even after removing the extra metal over the dielectric. Even the possibility may be less but we have to make sure that there should not be any particles over the surface. For that we have to do some extra polishing (may be few more rotation of polishing pad). This is known as over-polishing.
Note: This over polishing is one of the reason for Erosion and Dishing.
If you are okay with the above 2 concepts – Selectivity and Over-polishing, it will be too easy for me to explain the reasons of Erosion and Dishing during the CMP process.
I have already explained that when we are removing the Metal then all the parameters will be as per metal layer. When we do the over polishing (to make sure unwanted Metal is removed completely), then we are also doing CMP for Dielectric (but not in favorable environment). By doing this some dielectric also removed. But that will also remove some Metal (which should not be removed ideally). Refer below figure.
There are 2 type of metal wire.
- Wide metal wire
- Narrow metal wire with narrow Spacing.
In case of wide metal wire, overlap of polishing pad with Metal is more in comparison to narrow metal wire. From the CMP process point of view, remember one thing that polishing pad surface distorted during CMP process. For wide metal wire, pad asperity easily touches the Metal wire (copper wire) in the trench and scoops out soft Metal (Copper) between the harder dielectric.
So, during over polishing, polishing-pad can remove more Metal in case of Wide Metal wire (compare to Narrow Metal wire). This is what I have tied to explain in above diagram. Since for Dielectric it’s not a favorable environment, removal rate is less for Dielectric compare to Metal and that’s the reason you can see curve (dish type shape) in the Metal wire section. Obviously, for Wide metal this curve will be more compare to Narrow Metal wire.
This curve, non-presence of Good Metal, consider as defect or say manufacturing defect and known as Dishing.
I think now you can yourself figure out below points.
- More dishing in case of Wide Metal
- Less Dishing in case of Narrow Metal.
- Dishing has dependence on the Width of the Metal.
- Dishing has dependence on the surface of Metal in contact with the polishing pad. So if we want to minimize this, we have to reduce this overlapping or minimize this effect. For that we can do slotting in case of Wide Metal layer (If we can’t replace the wide metal layer with narrow Metal wire – it depends on design requirement).
Now lets’ take the scenario where both type of Metal wire present (Wide Metal wire and narrow Metal wire). (Blue color Metal wire)
In this case 2 concepts applies.
- Over polishing time.
- In case of wide spaced metal,
- Presence of small particle outside the defined area (area of Metal wire slot) can be considered.
- No Electrical shorting and other effect will be there.
- Over polishing will be there but not extra or say for less amount/duration.
- In case of narrow spaced metal
- Presence of small particle can result to electrical shorting, can increase the cap value or may affect the circuit in some other way.
- So we have to be extra sure or confirm that there is no particle remaining on the surface.
- This extra surety will result extra duration of over polishing.
- More over polishing means more removal of Dielectric layer from the design.
- Pattern Density
- As the pattern density increases, dimension of the Dielectric decreases.
- The pressure on the dielectric also increases which enhances the aggressiveness of the slurry toward the dielectric and assist in mechanical abrasion.
- These combined effects account for the dramatic increase removal of Dielectric from the surface.
Same thing I have tried to explain in the Diagram. You can see that when metal wire is closely placed, Height of the Dielectric decreases. And that effect is known as Erosion. I am not saying that “widely placed wire” don’t suffer with this effect but comparatively it’s less.
Now if the pattern density is different in different area of the chip then Erosion effect will be different as per that. In that case we can see Erosion Variation throughout the chip. To decrease the Erosion variation (within the chip), the pattern density should be uniform with in the chip. To achieve this, we do the dummy fill insertion and make sure uniform density can be maintained. Erosion increases considerably as the density of the pattern increases, regardless of the line width.
Let me summarize few of the things (which we have discussed till now).
Copper Dishing is defined as the difference in height between the center of the copper line – i.e. the lowest point of the dish – and the point where the SiO2 levels off – i.e. the highest point of the SiO2. It is caused by two factors:
- polishing pad bends slightly into the recess to remove copper from within the recess and
- Softer material is polished faster than the surrounding hard material.
The SiO2 Erosion is a thinning of the SiO2 layer resulting from the non-zero polish rate of SiO2 during over-polish step.
The SiO2 Erosion is defined as the difference in the SiO2 thickness before and after the polish step.
Copper dishing is strongly feature size dependent, but rather insensitive to pattern density. Oxide erosion, on the other hand, is strongly pattern density dependent, but feature size independent.
From the above discussion it is sure that over polishing is main cause of all the CMP effects. So if we can control it (Over polishing time), we can minimize these variations in the manufacturing. There are several methods – Just discussing few, so that we can understand it (as such it’s out of our scope).
CMP END Point detection: I am just discussing 2 methods in this category.
- Monitoring the Motor Current.
- Optical End Point:
Monitoring the Motor Current. When CMP process closing to end, polish pad start to contact and polish underneath layer
- Friction force start to change
- Current of the polish head rotary motor will change to keep constant pad rotation rate
- Monitoring the change of motor current can find endpoint of the CMP process.
- The moment you can figure out this peak in the motor current, you can program your machine that it shop.
- It will help not to do the over polishing.
Optical End Point: Different material has different reflectivity (intensity of light reflected).
- Let us suppose you are getting some intensity of light after reflection with the help of Metal.
- You want to do planarization of Metal.
- Keep monitoring the reflectivity and do CMP.
- The moment it changes (because of Dielectric), you can stop the CMP process.
- Again, it will help not to do over polishing.
Particles and Defects: Particles and defects cause irregular topography on wafer surface
- Scattering incident light
- Monitor particles and defects by detecting the scattered light
These particles can be detected with the help of light scattering phenomenon.
This phenomenon is used in the below method
- Laser beam scans wafer surface vertically at one focus of elliptical mirror and a photodetector is placed at another focus
- Moving wafer, and collecting scattered light to detect tiny particles and defects
- Mapping particle/defect locations on the wafer surface
Reference: SIMTech Technical Report (PT/01/003/JT) “Chemical Mechanical Planarization” by “Dr Wang Zhengfeng , Dr Yin Ling , Ng Sum Huan , Teo Phaik Luan”