Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

Saturday, February 27, 2016

Parasitic Extraction: Introduction

What do you mean by Parasitic Extraction ?

Basically it's a link between 2 domains: Physical Domain and Electrical Domain. Or you can say that it's uses the Physical Information (like Shapes of the design) and provide the Electrical information (Connectivity , Resistance, Capacitance and Inductance).
Everyone of us know very well that Timing is critical for the design and it has dependency on the delay of the network. For calculating the Delay, we should be aware about the Resistance/Capacitance of the Network/Devices. So question is how can we extract this info (R/C) from a layout (which user design/draw) and I can say this very confidently that "Parasitic Extraction do this job efficiently".

So, basically Parasitic Extraction provide the information about the Parasitic Devices which is not included as a part of original circuit design. But these Parasitic Devices effects the Circuit performance in several ways. There are chances that because of these Devices, your circuit stop working or not meet Design Specification. Few examples are:

Effect of Parasitic Devices on Circuit Design:
• Extra Power Consumption
• Violate the Power specification
• Extra power dissipation can increase local Temperature which can effect other parameters
• Effect the Delay of circuit
• which can cause of Timing Violation
• Can impact IR Drop
• Reduce the Noise Margin
• which can cause Logic Failure
• Increase Signal Noise which can
• Also Change the Logic of the signal (0 to 1) or (1 to 0) - Means Logic Failure
• Introduce extra/unwanted delay which can impact the Timing numbers
• Speed up the signal which again impact the Timing Numbers
• Increase IR drop on power Supply lines that affects Delay

Before we understand other details of this, it's important to know where all we can use it (Parasitic Extraction):
• During Static Timing analysis:
• Parasitic Extraction help us to find out the R/C(Delay) of the Network.
• Delay Help us to do Timing Analysis.
• During Noise Analysis, Crosstalk Analysis, Signal Integrity Check :
• For Noise and Cross Talk analysis, it's important to know the relationship between 2 wires. How these wires transfer the information between themselves.
• Coupling Capacitance is the mode of interaction between them. Parasitic Extraction help us to find the Coupling Capacitance between 2 wires, which help us further to do SI (Noise/Cross talk) Analysis.
• In Logic Simulation:
• For Logic Simulation, we need to know Delay information + Connectivity Information.
• Parasitic Extraction provide the Netlist which has information how different Nets and devices are connected with each other. It help us to do Logic Simulation.
• During IR Analysis:
• For IR analysis, Resistance is one of the Important parameter.
• Parasitic Extraction outputs "Resistance of the Network" which help in IR Analysis
• Substrate Noise Analysis :
• In the analog design, a lot of Noise through the Substrate passes to other part of the design.
• We know that any channel through which any information can transfer have finite resistance. Parasitic Extraction also help to find the Resistance of the Substrate, which help further into the Substrate Noise analysis.

Below 180nm, these parameters (Interconnect Delay and Coupling Capacitance) plays a majority of role, so it's very important to extract this information correctly. But as we all know- Accuracy always hit performance (runtime). More accurate results means more runtime. So there are several ways or say mode in every Parasitic Extraction tool provided by different Vendors so that user can extract only required information. Few of them are:
• Extract Resistance Only
• Extract Capacitance Only
• Extract Resistance and Capacitance both

Capacitance also are of 2 types (or say "Mode") :
• Decoupled Capacitance
• Coupled Capacitance

So, you can use any combination to Decrease or Increase the Runtime. It depends on what you want and at which stage.
You may be thinking that what are these Coupled and Decoupled Capacitance. Please refer Article "Coupled and Decoupled Capacitance Extraction Mode".

Runtime of the Extraction can also be decreased by compromising with the Accuracy of the Results. As we all studied in our college days that there are 2 type of network
1. Lumped Network
2. Distributed Network
Distributed Network is consider more accurate compare to Lumped Network. So same things apply here also. As much as our Network is distributed, there are chances of more accurate results. As much accurate our results - we will get accurate timing information. So in short it's important to model the Circuit as accurate as much possible. but accuracy impact the Runtime also. So Extracted Tool provide us to control the level of distribution. For example - 1 wire of 10nm can be divided into 10segment or 20segment or may be just 1 segment. Each segment will have their R and C component. using this technique, we can control the Runtime and Accuracy of our output Netlist.

Apart of Above extraction mode, Runtime of each Extracted Tool also depends on several parameters
1. Design Size
2. Process or Technology Node
3. Output format
4. System Configuration (Or say available Machine Resource) like No of CPU, Memory, Machine Type.

These parameter are mostly out of control from the designer side. Designer can play little bit but can't change a lot. Like If my design is on 45nm and have complex routing, Designer can't change it. EDA tool should be good enough to handle it. And that's the reason- Every EDA group work day-and-night to meet customer requirement.

We will discuss more about Parasitic Extraction, Parasitic Devices and other details more in this series of Articles.

Coupled and Decoupled Capacitance Extraction Mode

During the Parasitic extraction we have a lot of modes to decrease the runtime and extract the desired information. For Capacitance extraction we have 2 sub_modes.
• Coupled mode
• Decoupled Mode

If any signal is passing through a wire, it can effect near by wire too. We all know that this is because of charge difference between 2 wire, which help these 2 wire to form a Capacitance.
More clearly if you want to understand - Lets assume there is a Net A and Net B. These two nets are near by. We put a voltage spike on Net A, Net B will get a charge Injection due to the voltage changing on Net A.
Now this Process effect the Signal Flowing through Net A as well as on Net B. In case of Net A, it's consider a Loading effect (Because main signal is flowing through A). In case of Net B, it's consider a noise or Cross talk effect because main signal was flowing though Net A but it effect the signal flowing through Net B.

Coupling and Decoupling mode are related to this particular Cap (Cap between Net A and NetB)

Coupled Mode:
Net-to-net parasitic capacitances are extracted and be part of output Netlist separately. Basically it replicate the Practical scenario and helps in SI (Signal Integrity) analysis.

E.g:
C1 NetA NetB 2fF.

Decoupled Mode:
Net to net Capacitance are lumped to ground. I am not saying that this cap will not be extracted but I am saying that this Cap is not going to be part of output netlist as a separate Cap value. This Cap will be the Part of Total Cap (Cap with respect to Ground). So in place of 1 Cap value between Net A and Net B, we will get 2 Cap value.

E.g :
C1 NetA GND 1.1fF
C2 NetB GND 0.9fF.

Capacitive coupling effects are not there in this mode. So You can't use such netlist during the SI analysis. It's comparatively less accurate but it can speed up simulation time a lot.

Just trying to explain the same with one more example.
There are 3 Net. "NetA, NetB, NetC". Different Capacitances are:

NetA -> NetB : 3fF
NetA -> NetC : 3fF
NetA -> GND : 8fF
NetB -> GND : 8fF
NetC -> GND : 8fF

Here NetB and NetC are far away, so not added the Coupling between them. All Nets are of Same Type, so you can see the Same CAP value.

When you extract the Capacitance in the Coupled Mode, Following is the Netlist.

C1 NetA NetB 3fF
C2 NetA NetC 3fF
C3 NetA GND 8fF
C4 NetB GND 8fF
C5 NetC GND 8fF

When you extract the Capacitance in the De-Coupled Mode, Following is the Netlist.

C1 NetA GND 11fF
C2 NetB GND 9.5fF
C3 NetC GND 9.5fF

What happen? Are you not able to figure out ?

CAP between NetA and NetB divided into 2 (here I am doing with equal part but it depends on Wire property and distance with Ground and all) 1.5fF each. Now this 1.5fF is added to NetB to Ground and NetC to Ground.
So value become 8 + 1.5fF = 11.5fF For Both NetB and NetC.

For Net A , it become 8 + 1.5fF (from NetB) + 1.5fF (from NetC) = 11fF.

Why, Setup Depends On Max Data path Delay and Hold Depends on Min Data Path Delay ?

Let me start with the important points those were the outcome of previous Article...
1. Setup and Hold Check is associated with the Capture Flip Flop and Capture Clock Edge.
2. Setup and Hold Time Create a window across the Capture Flip Flop and for proper operation of Flip flop, Data should be stable during that window.
3. Data launched by "Launch FF" (FF1) at clock edge "1" is going to capture by "Capture FF" (FF2) at clock edge "2" (Means Next clock Edge).
4. If data reach D2 pin of FF2 with in Setup time window of Next Clock Edge, That is consider a Setup Time Violation. In below figure, if the time when B reaches D2 lies in Gray area across edge "3" (or the time when A reaches D2 lies in Gray area across edge "2"), it's a Setup Violation for Timing path "Path1".
5. If data reach D2 pin of FF2 with in the Hold time window of Same Clock Edge, That is consider a Hold Time Violation. In the below figure, if the time when B reaches D2 lies in Red Brown area across edge "2", it's a hold Violation for Timing path "Path1".
6. Remember - If "B" reaches Red brown area across edge "2", it will unstable Data "A" And as per the Hold requirement - A should be stable in the Red brown area across edge "2".
7. From the above 3 points (#4,#5,#6), it's clear that Data "B" has a window between Two clock edge ("2" and "3") in which if it reach D2 pin of FF2, there will be no Setup and Hold Violation. And this is our requirement.

Now, you can easily say that data "B" will take a certain time to reach from Q1 to D2, you will calculate that part and you can easily figure out whether "B" is in Gray area (across "3") or Red Brown Area (across "2"). Once you know this information, it's very easy to fix setup and hold Violation. Then Why do People always so much worry about this ? Why, Fixing Setup and Hold Violation is so complex?

Whatever you are saying is 100% correct but you have added a certainty in above approach ("B" will take a certain time to reach from Q1 to D2). This certainty has a lot of hidden conditions.

You can understand this in the way - if someone ask you - How much time you will take to reach from location "X" to Location "Y" ? And you have to give specific numbers. I am sure you will answer something like this (I took some random numbers for clear understanding).
• It will take 60min to reach if I am driving a Car with a constant speed of 50miles/Hr and No Traffic Signal Stops me.
• It will take 65min to reach if I get all the Traffic Signal RED.
• It can be faster( near about 45min), if I ask My driver to drive my Car.
• In case of Peak Hr, there will be a lot of Traffic on road and during that time, It will take approx. 90min. And it doesn't matter whoever drive

I am sure you got my point. :) Now from Data point of view, If I will ask you same question once again "How much time Data "B" will take to reach D2 pin from Q1 pin ?" :) :)
Now, your answer will be some thing like this (if not - means you didn't get my point in above example :) :) ).
• It depends on previous data and current data. Means whether Data switches from 0->1, 0->0, 1->0 or 1->1.
• It depends on What type of Cell are we using ?
• It depends What's the environment condition? Is there anything which can change the Delay of the Path ?
• It depends if Path is fabricated as per your specification (no manufacturing defects).
• It depends on which PVT conditions we are calculating the delay?

So basically, you will come up with a lot of conditions and you will ask back a lot of questions before calculating and providing a specific value. There may be few questions which I can answer with definite numbers but lot of answer will be in a range. Like (my answer may be something like this)
• Environment temperature can vary between -40deg to 120deg.
• There will be only 2 type of transition between the Data in this path (0->1 and 1->0).
• We will use only LVT cells but that can be of any driving strength.
• I can't give you the guarantee that there will be no Manufacturing Defects, but yes foundry provided a "range" of data to model those defects.
• We have figured out 10 PVT corners for which this timing path should work without any violation.

So what's does it mean -Even, I have all the Answer but every thing is in range. Because I don't know who will be the end use?, in which environment condition this chip is going to use (Timing path belongs to whatever chip)?, What will be the condition of chip after 2 year?, During the manufacturing whether it will be in the middle of the wafer or at the edges? I myself have a lot of uncertainty in my answer.
As inputs are in range - you will calculate the delay (Time take by "B" to reach Q1 to D2) using all the combination and I can bet that you answer will be in a range not a certain value. :) :)

By now, you should be clear - why in real world we don't talk about the specific numbers. :):)

So it means "B" has a min and max time to reach D2 pin.
Min value means - as per the different combination of Input, "B" will not reach D2 pin before this minimum value.
Max value means - as per the different combination of Input, "B" will not reach D2 pin after this maximum value.

So now lets revisit the Setup and Hold Check definition and requirement (along with the Diagram).

In the above figure, Data "B" is divided into a range (from Bmin to Bmax). Now, you can easily visualize the condition of Setup and Hold Violation.

Setup Violation:
• If "Bmax" lies in the Gray area across Edge "3", it's consider a Setup Violation. OR
• I can say that if Data Range (Red area across data "B") overlap Gray area across Edge "3", it's a Setup Violation.
• It means for Setup Check, we consider "Maximum Data Path Delay" (In above example, it's "Bmax").

Hold Violation:
• If "Bmin" lies in the Red Brown area across Edge "2", it's consider a Hold Violation. OR
• I can say that if Data Range (Red area across data "B") overlap Red Brown area across Edge "2", it's a Hold Violation.
• It means for Hold Check, we consider "Minimum Data Path Delay" (In above example, it's "Bmin").

Now 1 interesting question - Is it possible that Bmin and Bmax will overlap Gray (across Clock Edge "3") and Red_Brown (across Clock Edge "2") area at the same time ? Yes It is... And if this Possible - what does it mean ???
Same path has Setup and Hold violation at the Same Time.

I think, I am able to successfully answer both questions which you have asked me in the end of Previous Article.

So for Doing the Setup and hold checks, you have to give a lot of inputs to the Timing Analysis tool and then it will do the calculation, figure out the min and max delay of the Data path and check whether there is any overlap or not with the Setup and Hold Window across The Clock Edge. If we miss any input, report provided by the Timing analysis tool will not be correct. That's the reason we do the Timing analysis several time during the whole design Cycle. As we move forward, we get more clarity about the inputs/condition, we feed those inputs to timing analysis tool and try to fix setup and hold violation incrementally.
Other flip side of this - It's not a easy job and Run time will be huge.

So the Question come - How can we reduce the complexity of the Inputs and also decrease the Analysis time. For this, different Timing tools have different methodology but a very common way is "Adding the Pessimism in the calculation of Delay Value". This helps even in providing less input (or say impose less conditions) to timing tool and it become fast.

I am not suppose to mention that:
After the Pessimism, Min value of Data path Delay < actual min_value of Data path Delay.
After the Pessimism, Max value of Data path Delay > actual max_value of Data path Delay.

If you are able to fix Setup and Hold Violation in this condition - means It's already ready for actual value. But problem comes when you are not able to fix with these Pessimistic values. Then we have to debug a lot (or say dig a lot) and has to figure out
• Whether these are real violations or not?
• If These are real violation, what's the root cause of that and what's the solution of that?

We will discuss in detail about these questions in next Article.

Setup and Hold Check

In this series of articles, I will discuss Advance topics related to Setup and Hold Violation. I will try to explain following things
• How does Timing Tool calculate/report Setup and Hold Violation ?
• What are the different Reasons for Setup/Hold Violation reported by Timing Tool? Those are Real violation or limitation of tool?
• Timing Tool take pessimism approach for calculating Setup/Hold violation, How to debug that part before reaching to conclusion that these are real or false Setup/Hold Violation.
• If there are several Setup/Hold violation, How to narrow down and find out the real cause of the Issue.?
• What are different methods to fix these violations ?
• Which approach/Method we should use in which case?

There are list of other questions/confusions, which I will try to cover in this series.
Now, lets start With the same Question "What is setup and Hold Violation?" :)

Above diagram is very basic Diagram which we always use in STA. In the above diagram,
• There are 2 Flip flops - FF1 (Launch FF) and FF2 (Capture FF). These Capture and Launch are with respect to Timing path (Path1).
• 2 Clocks : CLK1 and CLK2 - I assume the ideal one (Means No Skew) for simplicity purpose.
• There is a small delay between CLK_S (source Clock) and CLK1/CLK2 because of Buffer (Buf2).
• Every Clock edge is marked with number, so that I can easily refer those number in place of saying "first edge or second edge".
• Net delay, we are considering Ideal right now.

We know very well that the data launched at Clock Edge "1" by the Launch Flip flop (FF1) is going to capture at Clock edge "2" by the Capture Flip Flop (FF2).
Note: If you don't able to understand this concept, please read the Static Timing Analysis Series.

Setup and Hold Checks are related to Capture Flip Flop. It means we have to understand These concept from the Clock edge at the Capture Flip Flop.
In the below figure,
I took the 2nd Edge of the CLK2 (CLK2 is the capture Clock for Capture FF2), it will help us to understand more clearly.
Data launched by CLK1 (which is associated with Launch FF) at edge "1" is "A" and at edge "2" is "B", which reach at "D2" as per the diagram.
Setup Time and Hold Time of FF2 is marked by Gray and Brown box across the CLK2.

As per the Setup requirement of FF2 - Data "A" should be stable at "D2", "Setup time" before the "2" clock edge of CLK2.

As per the Hold Requirement of FF2 - Data "A" should be Stable at "D2", "Hold Time" After the "2" Clock Edge of CLK2.
• There is only one data which can make "A" unstable after the "2" Edge of CLK2 and that's the "B" (which is launched at "2" Edge of CLK1), if it's reaches at "D2" with in the hold time range.
• So I can also say that data "B" should reach at "D2" only "Hold Time" After the "2" Clock Edge of CLK2.
• In the above example, "B" is outside the Brown Box (correspond to Hold time), it means "A" will be stable during that time.

And that's the reason,
During the Setup violation - We talk about:
1. The Same Data: In above example "A".
2. Two different Clock edges: In above example - "1" of CLK1 (Launched "A") and "2" of CLK2 (Captured "A").
During the Hold Violation - We talk about:
1. The Same Data: In above example "B".
2. Same Clock edge: In above example - "2" of CLK1 and CLK2

If "A" is in the Gray box - It's a Setup Violation.
If "B" is in the Brown Box - It's a Hold Violation.

Theoretically, above things looks good but if we are not providing any input data to the design, how come Timing tool figure out what data is launched by CLK1 at "1" or at "2" ? I think you may have this question. If that's the case, how can Timing tool do the calculation for Setup and Hold Violation. :)

In the above figure, "A" is the data launched by CLK1 at "1" and "B" is data launched by CLK1 at "2" and diagram shows the time instant when they have reached at D2. Now we are only talking about the Capture Clock CLK2. We have picked 2 edges "2" and "3" (I can also pick "1" and 2" but these edges will help you to understand the concept easily).

If Data "B" reach early (at D2),there are chances that it may come in the Brown Part (of Edge "2") - Means make "A" unstable - That Means Hold Violation in this path.

If Data "B" reach late (at D2), there are chances that it may come in the Red Part (of edge "3") - Means Not stable before Setup Time - That Means Setup Violation in this path.

During the Timing Analysis -
• Tool know the frequency of Clock - Means Time period - Means It know the Time difference between the 2 Clock Edges. In above example, if "1" is the reference that tool know very well when "2" and "3" will come.
• How much Time Data will take to travel from Q1 to D2 - depends on the Delay of the circuit. Which Tool know very well.
• From The Flip Flop Library, it can easily extract the Setup and Hold time.
• Whether Flip flop is Negative edge triggered or Positive edge triggered, can easily extracted by Flip Flop Library.
• Other information, Like Net delay, Clock path Skew depends at what stage you are doing the Static Timing analysis and accordingly tool uses those information.
So, in short Timing Tool have all the information which are necessary to do the Timing checks. It don't need the any signal travel information. Analysis result also not going to change if you give input 101 or 010 or 111 or 000 ..etc.

In general, with the help of Time Period, Clock Skew (if it's there), Setup and Hold Time - Timing Tool come up with a window (min and max value) for the Data path Delay.

If Delay is less then the MIN value of that Range - It's a Hold Violation.

If Delay is greater then the Max value of that Range - It's a Setup Violation.

I am sure you are clear what I have tried to explain you. But now you may have few other questions.
• Delay of a path should be a single value, then why we talk about the max/min delay of a path, maximum delay of data path for Setup check and minimum delay of data path for Hold delay ?
• As per above explanation, it's very clear that in your circuit for a timing path either there should be a Setup violation or Hold violation. But How come you have seen/heard setup and hold violation at the same time?
I will explain this part in the next coming Articles in more detail.