## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Saturday, February 27, 2016

### Parasitic Extraction: Introduction

What do you mean by Parasitic Extraction ?

Basically it's a link between 2 domains: Physical Domain and Electrical Domain. Or you can say that it's uses the Physical Information (like Shapes of the design) and provide the Electrical information (Connectivity , Resistance, Capacitance and Inductance).
Everyone of us know very well that Timing is critical for the design and it has dependency on the delay of the network. For calculating the Delay, we should be aware about the Resistance/Capacitance of the Network/Devices. So question is how can we extract this info (R/C) from a layout (which user design/draw) and I can say this very confidently that "Parasitic Extraction do this job efficiently".

So, basically Parasitic Extraction provide the information about the Parasitic Devices which is not included as a part of original circuit design. But these Parasitic Devices effects the Circuit performance in several ways. There are chances that because of these Devices, your circuit stop working or not meet Design Specification. Few examples are:

Effect of Parasitic Devices on Circuit Design:
• Extra Power Consumption
• Violate the Power specification
• Extra power dissipation can increase local Temperature which can effect other parameters
• Effect the Delay of circuit
• which can cause of Timing Violation
• Can impact IR Drop
• Reduce the Noise Margin
• which can cause Logic Failure
• Increase Signal Noise which can
• Also Change the Logic of the signal (0 to 1) or (1 to 0) - Means Logic Failure
• Introduce extra/unwanted delay which can impact the Timing numbers
• Speed up the signal which again impact the Timing Numbers
• Increase IR drop on power Supply lines that affects Delay

Before we understand other details of this, it's important to know where all we can use it (Parasitic Extraction):
• During Static Timing analysis:
• Parasitic Extraction help us to find out the R/C(Delay) of the Network.
• Delay Help us to do Timing Analysis.
• During Noise Analysis, Crosstalk Analysis, Signal Integrity Check :
• For Noise and Cross Talk analysis, it's important to know the relationship between 2 wires. How these wires transfer the information between themselves.
• Coupling Capacitance is the mode of interaction between them. Parasitic Extraction help us to find the Coupling Capacitance between 2 wires, which help us further to do SI (Noise/Cross talk) Analysis.
• In Logic Simulation:
• For Logic Simulation, we need to know Delay information + Connectivity Information.
• Parasitic Extraction provide the Netlist which has information how different Nets and devices are connected with each other. It help us to do Logic Simulation.
• During IR Analysis:
• For IR analysis, Resistance is one of the Important parameter.
• Parasitic Extraction outputs "Resistance of the Network" which help in IR Analysis
• Substrate Noise Analysis :
• In the analog design, a lot of Noise through the Substrate passes to other part of the design.
• We know that any channel through which any information can transfer have finite resistance. Parasitic Extraction also help to find the Resistance of the Substrate, which help further into the Substrate Noise analysis.

Below 180nm, these parameters (Interconnect Delay and Coupling Capacitance) plays a majority of role, so it's very important to extract this information correctly. But as we all know- Accuracy always hit performance (runtime). More accurate results means more runtime. So there are several ways or say mode in every Parasitic Extraction tool provided by different Vendors so that user can extract only required information. Few of them are:
• Extract Resistance Only
• Extract Capacitance Only
• Extract Resistance and Capacitance both

Capacitance also are of 2 types (or say "Mode") :
• Decoupled Capacitance
• Coupled Capacitance

So, you can use any combination to Decrease or Increase the Runtime. It depends on what you want and at which stage.
You may be thinking that what are these Coupled and Decoupled Capacitance. Please refer Article "Coupled and Decoupled Capacitance Extraction Mode".

Runtime of the Extraction can also be decreased by compromising with the Accuracy of the Results. As we all studied in our college days that there are 2 type of network
1. Lumped Network
2. Distributed Network
Distributed Network is consider more accurate compare to Lumped Network. So same things apply here also. As much as our Network is distributed, there are chances of more accurate results. As much accurate our results - we will get accurate timing information. So in short it's important to model the Circuit as accurate as much possible. but accuracy impact the Runtime also. So Extracted Tool provide us to control the level of distribution. For example - 1 wire of 10nm can be divided into 10segment or 20segment or may be just 1 segment. Each segment will have their R and C component. using this technique, we can control the Runtime and Accuracy of our output Netlist.

Apart of Above extraction mode, Runtime of each Extracted Tool also depends on several parameters
1. Design Size
2. Process or Technology Node
3. Output format
4. System Configuration (Or say available Machine Resource) like No of CPU, Memory, Machine Type.

These parameter are mostly out of control from the designer side. Designer can play little bit but can't change a lot. Like If my design is on 45nm and have complex routing, Designer can't change it. EDA tool should be good enough to handle it. And that's the reason- Every EDA group work day-and-night to meet customer requirement.

We will discuss more about Parasitic Extraction, Parasitic Devices and other details more in this series of Articles.

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