## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

# Introduction and Source Of Clock Skew

It's very important to understand the Skew and how it impact the timing analysis. Few different flavor of Definition. :)
• It's a difference between the clock arrival time across the chip.
• It's the time delta between the actual and expected arrival time of a clock signal.
• Clock skew is the timing differences between signals in a clock distribution system
• Variation of arrival of clock at destination points in the clock Network.

As you can see in this pic, positive edge of both the clock signal (CLK1 and CLK2) has some time delay even when there is Same clock source (CLK_S). This Time delay is known as CLOCK SKEW.

There are lot of thinks which I was trying to write down here but later I decide to record that part. Please refer these videos for more detailed Understanding about the Clock Skew.

### Source of Clock Skew

In general Clock skew has 2 Distant sources.
1. Clock Driver or Clock Buffer
2. Clock Distribution System

Clock Driver and Clock Buffer:
Clock Buffer is a special type of Buffer which is required to keep the Transition with in a certain range. We will discuss this in detail in terms of Layout and all but important thing these are designed specially for Clock path. Ideally all the clock buffer / clock driver, all the internal circuit elements should matched perfectly so that the propagation delays become identical. In a practical clock driver there are many variables which can effect the propagation delay when though paths are equivalent and these effects /parameters contribute to skew. Few of them are:
• The layout and electrical characteristics of the gate components
• Output Load Vs Current characteristic
• Input Transition Vs Delay Characteristic
• Different Resistance of Internal VIA and Metal wire
• The location of those components relative to ground and VCC
• Different Capacitance which can effect Charging and discharging time
• Internal Coupling Cap difference
• In Die Process, Voltage, Temperature (PVT) variation
• Different clock buffers with different channel lengths
• Local drop in voltage leads to increased buffer delay
• Device mismatch across die
• Hot spots lead to increased gate delay

Clock Distribution System:
This is second source of clock skew which is playing a significant role in lower nodes. The Clock buffer is important in clock distribution but how that distribution is done is very important. If it's uneven, then you will notice a skew between 2 Clock. Practically what ever you do, you can't design 2 wires with all environment identical. And because of this difference you will see a difference in Net delay, which contribute in SKEW. Few source of difference are:
• Wire Coupling
• Coupling will be different on different clock routes.
• Near by Signal Lines can distort (add delay) the Clock signal because of coupling effect.
• Nearby Power Line can also effect the Wire coupling.
• RC Mismatch
• Clock routes not all of equal length.
• Latches or Flip Flop not all equal distance from Clock buffer.
• Process, Voltage, Temperature (PVT) variation
• Hot spots lead to increased wire delay.
• Manufacturing Effects can change the width/thickness of wire, which result different delay.
• Unequal Buffering
• Unequal buffering can cause additional skew due to rise time/fall time dependent delay in buffers.
• Change the Load of previous Stage.
• Contribute in different transition time means different wire delay.

In summary, I can say that if you need to understand the Sources of Skew, you need to understand how many type of delays are there ? How delay changes with respect to different parameters like output load, Input transition, Temperature and all.
You can refer few of my previous articles which can give you some direction to think. I will see later, if there is any need to add more content.

Delay related Articles:

If you want to understand how Variation during the fabrication can change the Metal width / Thickness, which are related to R and C value (Delay), then you can refer below series of Manufacturing Effect.

PS: I hope above articles help you to understand the Source of Skew. Even if you have any question, Drop me message.

### Interview Question:

There are lot of questions can be asked on this topic. Few I am listing here. All the Answer are hidden in above material. :)
1. What do you mean by Clock Skew
2. Skew is related to specific clock domain or it can be across any Clock domain ?
3. What are the different reason for Clock skew?
4. I have instantiate same Clock buffer in each of 2 clock path, is there any possibility of Clock skew even in that case ?
5. How can variation in Power supply contribute in Skew?
6. Cell Delay has dependency on Input Transition and Output Load. But if on 2 different clock, Buffers are places at the same distance and output load is also same, whether there is any possibility for Skew even in that case ?

Note: Basically, Most of the question will be related to Delay and how that changes with different parameters.

In Next Article, we will discuss More about Skew Like "Different type of Skew", "Impact of Skew on Timing", "What are different Methods for reducing Skew", "What are different Methodology of Design which can help us to reduce the effect of Skew" and a lot more. Stay tune and enjoy reading.