Classification Of Clock Skew
In the previous Article, we have discussed about the Skew and the Source of Skew. In this article we will talk about Different Type of Skews.
Classification Of Skew:There are different ways we can classify Skew. For me, it's very difficult to divide those into different bucket and come up with a tree like structure. But still I am making an effort.
Internal (Intrinsic) And External (Extrinsic)
- Internal Skew:
- It is governed by the Devices or Gates.
- Difference (in time) introduced because of mismatch of propagation delay and transition delay of 2 identical devices or gates.
- External Skew:
- This is the difference introduced because of unbalanced Net length or output loading or any other effect (like delay added because of cross coupling).
As we know, it's not possible to fabricate 2 gates identical in nature. Even though if you take care, there will be some difference in fabrication. This difference can contribute into the propagation delay of the gate under same external environment conditions.
So if we keep all the external factors (parameters) constant/identical, The difference between the propagation delay of 2 identical gates at the output pin, at identical transition is known as Process Skew .(i.e., compares tpd(LH) versus tpd(LH) or tpd(HL) versus tpd(HL) for any two outputs).
For example, if the propagation delay of the fastest output (tpd(LHn)) is 2 ns and that of the slowest output (tpdLH1) is 2.165 ns, then the output skew is: tpd(LHn) - tpd(LH1) = -165ps.
- Part-to-Part Skew: If these 2 gates are in different devices then these are known as Part-to-Part Skew. This is also known as Package Skew.
- Output Skew: If these 2 gates are part of same device then are termed as Output Skew. Also Known as Pin-To-Pin Skew.
Pulse skew (tsk(p)) is the magnitude of the time difference between the high-to-low (tPHL) and the low-to-high (tPLH) propagation delays. Pulse skew is sometimes referred to as Duty Cycle Skew.
tsk(p) = | tPHL − tPLH |.
As such the Time Period will be same but the Duty Cycle changes because of Pulse Skew. It plays a very important role when in the circuit we are going to use both Negative and Positive edge of the Clock for Flip flop triggering.
In the Below Figure we have used a Clock Buffer, A represent the Input side and B represent the Output side.
Positive and Negative Skew:
Skew can be positive or negative on how the reference clock is chosen. Means if you do A-B > 0 then obviously B-A < 0. So if A is reference, Skew is Positive and if B is reference Skew is negative.
Remember - While calculating the Skew - we do Capture clock delay - Launch Clock delay. So from above sentence don't be confused that it's just a matter of "How you subtract". :) Below 2 figures explain how Positive Skew can be converted into Negative Skew.
Note: This is the Normal circuit we have studied till now. All the skew in this Circuit (above) are Positive.
Note: This circuit is same as the previous one, only difference is the direction of the Clock Vs Direction of the Data flow.
Above figure can help you to understand the basic difference between the Negative and Positive Skew. Now Question come - why we will do this. We will discuss later on in detail that Negative Skew helps in fixing Hold Violation. But there are several other cases where we will not intentionally reverse the direction of Clock but because of Clock distribution Network, it can happen automatically. Below 2 figures are self explanatory. :)
Here you can see very clearly that Clock is entering from the Middle. Right hand side's Flip flops have Positive skew and left hand Side's Flip flop has Negative skew. No one did this intentionally but it just happened because of CTS (Clock tree synthesis) and small negligence from the designer. :)
In the above figure it's clear that Clock tree was good but just because of 2 branches are communicating with each other (which is very normal), Negative Skew scenario developed between FF7 and FF8.
Inter Clock Skew:
When the clocks are in different domains, this is known as Interclock skew. Interclock Skew exists between two registers with different clocks.
Intra clock Skew:
When the clocks domain is same, skew is known as Intra Clock Skew.
In the above figure,
Skew between FF1 and FF2 is Intra Clock Skew.
Skew between FF3 and FF4 is Intra Clock Skew.
Skew between FF2 and FF3 is Inter Clock Skew.
I am sure I am not suppose to explain this. :)
In the next article, we will discuss about the effect of the Clock Skew in our Timing Analysis. We will also discuss Different Methods to reduce the Clock Skew between Capture and Launch Flip flop.