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Sunday, October 22, 2017

Physical Design Interview Questions (Part 2)


Second part of this series. There are few sets of questions which is very common from Physical Design Interview point of view.
One of my Student shared below questions with me and as I always do - Sharing with everyone. :) He told me that he got offer from 6 service based companies after practicing only these questions. I haven't validated his statement and going with his words. :)

Note: Not mentioning the Answer of these questions right now. But I will do that later on. If anyone of you can do this for me or others (in lesser time compare to my time)- that will be great. I will explain these Answers one by one in detail fashion, so obviously it will take time. :)

Third Set of questions (Asked in third Company)
Remember- first 2 set of questions already covered in previous article.
  1. What are the inputs given to PnR / What it contained?
  2. What are things will you do in data-setup?
  3. How will you place macros?
  4. Let A, B, C, D are four macro in a block, A & B are in same hierarchy and they are communicating with each other, D is also in same hierarchy as A & B but not communicating with A & B. C is in different hierarchy but communicating with D. How will you place the macros?
  5. What are the reason behind congestion between the macros?
  6. How will you find the spacing between two macros?
  7. How will you resolve congestion inside Standard cell?
  8. What is power planning?
  9. How will you reduce IR Drop?
  10. What is CTS? How will you synthesis clock tree and what are clock tree optimization?
  11. What is pre-routing?
  12. What are the low power techniques we used for the submicron technology?
  13. In a timing check between 2 FF, hold slack is +2ns but setup is failed by -10ns. How will you resolve it?

These are few set of questions which has been asked in 3 companies (2 sets, I have already shared in previous article). I am sure - lots more can be asked. My intension to captured these questions at this place is not to provide a list of questions which can 100% help you to crack any interview but I want to show you a pattern of questions and the amount of preparation which you need to do.
Like I said in my previous article - "I am not saying that only these questions are sufficient for you to crack any PD (Physical Design) Interview, but I am 100% sure that these will help you to understand if your preparation is good enough and also provide you certain direction in your preparation."

Just wanted to share one incidence before I finish this article.
After my first article, one of my friend from VLSI Industry (working as senior PD manager) called me and asked if I am doing the right thing to captured all these questions.

His concern was - what if candidates don't have understanding about whole PD flow but they know (mug-up or remember) all these questions and answer all of them correctly. They can't survive in Industry for Long, so am I doing justification with them? :)

In reply of this - I just asked one question to him - Are you asking same set of questions everytime in a same sequence & wording? He got my message and I hope same with you all.

In case, you need my help to check whether you are ready for Interview or NOT, Please request for the MOCK Interview. We can connect and you are going to treat as Interviewee. After the MOCK interview, I will provide you detailed feedback.
Steps to request for MOCK Interview Sessions are below.
  1. Fill all details of this Form.
    Registration Form
  2. WhatsApp your NAME and Location at 9740033323.
  3. Book your 30min Slot
  4. After the Mock Interview - Get Detailed Feedback at your Mail id

BEST OF LUCK.

Sunday, October 8, 2017

Physical Design Interview Questions (Part 1)


There are few sets of questions which is very common from Physical Design Interview point of view.
One of my Student shared below questions with me and as I always do - Sharing with everyone. :)

Note: Not mentioning the Answer of these questions right now. But I will do that later on. If anyone of you can do this for me or others (in lesser time compare to my time)- that will be great. I will explain these Answers one by one in detail fashion, so obviously it will take time. :)

First Set of Questions (Asked in One Company)
  1. Draw APR Flow
  2. When we will place "Physical Only Cells"
  3. What are "Spare Cells" and why it is used?
  4. Why do you make clock as Ideal during floorplan & Placement Stage?
  5. What are the different Checks we do in the CTS stage?
  6. What if Setup is failed after manufacturing of chip?
  7. How will you fix Hold?
  8. What is the Importance of useful Skew?
  9. What are DRV Checks and why do we check that?
  10. What is the cross talk? How it will effect the performance?
  11. Cross delay or Cross talk noise is note generally. Why?
  12. A Blocks having 7 Metal layers and same block having 10 metal layer, which will function better and why?
  13. How will you define the shape of the Die?

Other set of questions (Asked in Second Company)
  1. Draw and Explain APR flow.
  2. How will you place Macro?
  3. How will you reduce congestion near I/O parts?
  4. Where will you implement partial blockage?
  5. What are checks you will do after each stage of PNR?
  6. What is Setup and Hold Time?
  7. Few problem based on Setup and Hold Calculation.
  8. What are the Timing check will you do apart from setup and hold check?
  9. What if Setup and Hold Both fails?
  10. How will you resolve Setup and Hold Issues?
  11. What are clock free targets and buffer constraints?
  12. How will you fix DRV?
  13. How will you do cloning?
  14. Which metal will you use for Power routing and Why?
  15. What are routing grids?
  16. What is Antenna Effect and how will you resolve it?
  17. What is Antenna Ratio?
  18. What is Latch up and How will you resolve it?
  19. How will you place TAP Cells and in which Stage will you place Tap cells?
  20. Why ENDCAP Cells are used ?
  21. What all Datas will be given to FAB after Tapout?
  22. Why Derates are used for Timing Calculation? Is it Good or Bad?

I was thinking to list down Companies name here but then realized what if they stop asking these questions. :) :) But Point is these questions are very much related to concepts of whole PD flow. I am not saying that only these questions are sufficient for you to crack any PD (Physical Design) Interview, but I am 100% sure that these will help you to understand if your preparation is good enough and provide you certain direction in your preparation.

In case, you need my help to check whether you are ready for Interview or NOT, Please request for the MOCK Interview. We can connect and you are going to treat as Interviewee. After the MOCK interview, I will provide you detailed feedback.
Steps to request for MOCK Interview Sessions are below.
  1. Fill all details of this Form.
    Registration Form
  2. WhatsApp your NAME and Location at 9740033323.
  3. Book your 30min Slot
  4. After the Mock Interview - Get Detailed Feedback at your Mail id

BEST OF LUCK.


Monday, October 2, 2017

Delay Interview Question (Part1)


Let's discuss the Delay concepts from Interview point of view. Several times it happen that Interviewer is going to ask certain questions and the moment you answer it - they will change the case or scenario without changing the Diagram or values. Few of the scenarios, I am going to discussing here. Remember - As a Interviewer - our intension is to check "how much you know" and "How much you can visualize from Tool perspective or real design point of view".

Example 1:



All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay = (1.25ns, 1.5ns)
OR gate (min, max) delay = (0.3ns, 0.4ns)

Note: These min and max delay numbers are not corresponding to rise and fall delay number.

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
This question is very easy. You have to understand only 1 thing, There are 2 paths and question is all about min and max delay between Q1 and D2.So, you have to calculate both min and max delay with respect to both the paths and then figure out which one is minimum or maximum out of 4 delay values.

Solution:
Path 1 (Min Delay) : 0.25 + 1.25 + 0.1 + 0.3 + 0.1 = 2ns
Path 1 (Max Delay) : 1.0 + 1.5 + 0.2 + 0.4 + 0.2 = 3.3ns

Path 2 (Min Delay) : 0.25 + 0.25 + 0.25 + 0.3 + 0.1 = 1.15 ns
Path 2 (Max Delay) : 1.0 + 1.0 + 1.0 + 0.4 + 0.2 = 3.6 ns

Overall Min Delay between Q1 and D2 = 1.15ns (From Path 2)
Overall Max Delay between Q1 and D2 = 3.6ns (From Path 2)


Example 2:



All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay = (1.25ns, 1.5ns)
OR gate (min, max) delay = (0.3ns, 0.4ns)

Note: These min and max delay numbers are corresponding to rise and fall delay number respectively.

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
Now this question become tricky. As per Note - I have mentioned that these min and max delays are actually rise and fall delay. If this is the scenario, we have to understand circuit and find out more accurate Min and Max delay between Q1 and D2. Remember, above numbers (Min and Max delay in Example 1) is also correct but we are talking about more accurate number. This is the only trick or say the intension of Interviewer to ask you this question with slightly change in wordings. :)

We have to do 2 type of analysis for each path - Rising & Falling signal analysis at D1 for both paths.

Rising Signal Analysis (For Path1):
  • Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
  • AND gate is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for AND gate => 1.5ns
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
  • OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for OR gate => 0.4ns
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 1 + 1.5 + 0.2 + 0.4 + 0.2 = 3.3ns

Falling Signal Analysis (For Path1):
  • Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
  • AND gate is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for AND gate => 1.25ns
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
  • OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for OR gate => 0.3ns
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 0.25 + 1.25 + 0.1 + 0.3 + 0.1 = 2.0ns

Rising Signal Analysis (For Path2):
  • Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
  • Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
  • Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
  • OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for OR gate => 0.4ns
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 1 + 0.25 + 1 + 0.4 + 0.2 = 2.85ns

Falling Signal Analysis (For Path2):
  • Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
  • Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
  • Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
  • OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for OR gate => 0.3ns
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 0.25 + 1.0 + 0.25 + 0.3 + 0.1 = 1.9ns

Solution:
Path 1 (Min Delay) : 2ns (Because of Falling Signal Analysis)
Path 1 (Max Delay) : 3.3ns (Because of Rise Signal Analysis)

Path 2 (Min Delay) : 1.9ns (Because of Falling Signal Analysis)
Path 2 (Max Delay) : 2.85ns (Because of Rise Signal Analysis)

Overall Min Delay between Q1 and D2 = 1.9ns (From Path 2 - Falling Signal Analysis)
Overall Max Delay between Q1 and D2 = 3.3ns (From Path 1 - Rise Signal Analysis)



Do you think that's all .. NO NO NO .. Still there are couple of scenario which can be asked using same figure. Always remember - Interviewer never stop like this. :) :) Stay Tune for Next Article of this series.

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