## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Monday, October 23, 2017

### Metal Layer Stack (Metallization Option) Part 1

There are different metal layers which we uses in our design. As we move down the technology node number of standard cells increases or you can say that number of connections increases drastically. As all of us know that these connection are made of Metal wire, it means number of metal wires increases. Below figure help you to understand the scenario.

Case1 : I didn't decrease the size of the chip (despite change in the no of standard cells per unit area) as we go down the technology node. You can see that number of metal wires increases. Silicon utilization improves with improved routability. But these numbers (standard cell) increases 4 times (per node if we are decreases the size by 1/2, overall area decreases by 1/2*1/2=1/4). With available options of metal wire in higher node, it's difficult to route the same design in lower technology node. And that's the reason as we go down number of metal wires increases (vertically also).

Case 2: This is the real scenario. As Technology node decreases, no of standard cells increases and also chip size decreases. So you can imagine how difficult it is to route the design with a single metal wire or say on a single level. That's the reason we have multiple levels of metal wires. These levels are in vertical direction. As we go down the technology node, these levels increases. So you can say that down the technology node, size of the chip decreases in one dimension (in 2D) but increases in other dimension (vertically). :) :)

 Technology Node Vs Routing Complexity

To take care about the above options, foundry provides different option of metal in every technology node. These options are based on metal width, space, thickness or sometime other parameters. (You will get more clarity as we discuss more).

### Type of Metal Wire

On the basis of Metal wire parameter or say property, foundry divide or say categorize different metals. These metal wire are named differently to distinguish from each other. Let's assume XYZ foundry have nomenclature of Mx, My, Mz, Mr. Different technology node will have different options. For example.

In Technology node X.

Mx:   First Inter-layer Metal:   Min_width = 0.1um & Min_space = 0.1um.
My:   Second Inter-layer Metal:   Min_width = 0.4um & min_space = 0.4um.

In Technology node Y.

Mx:   First Inter-layer Metal:   Min_width = 0.08um & Min_space = 0.08um.
My:   Second Inter-layer Metal:   Min_width = 0.18um & min_space = 0.18um.
Mz:   Top Metal layer:       Min_width = 0.4um & min_space = 0.4um
Mr:   Top Metal layer:       Min_width = 0.5um & min_space = 0.5um

In Technology node Z.

Mx:   First Inter-layer Metal:   Min_width = 0.05um & Min_space = 0.05um.
Mya:   Second Inter-layer Metal:   Min_width = 0.12um & min_space = 0.12um & thickness = 2800A
Myb:   Top metal layer:   Min_width = 0.12um & min_space = 0.12um & thickness = 3200A
Mz:   Top Metal layer:       Min_width = 0.4um & min_space = 0.4um
Mr:   Top Metal layer:       Min_width = 0.5um & min_space = 0.5um

Note: These min_width and min_spacing numbers are not related to any technology node. I just picked these randomly to help you to understand how different metal wires are categorized.

As we go down these available options increases. Like Mx, My, Mz, Mu, Mr, Mw and so on. For exact numbers of metal and their property plz refer foundry provided documents.

Foundry also recommend based on the uses of metal wire. Like few metal wire options with a relaxed pitch (minimum_width + minimum_spacing = Pitch) for power, clock, busses and other important signal distribution. Tighter pitched options for general signal routing. You can also see (In Technology Node Z) that Mya and Myb are also 2 different type of metal wire because their Thickness values are different (even though their min_width and min_spacing are same). So you can understand that as per the uses, foundry provides a lot of options. Now it's upto designer how to use those options.

Foundry provide this (above) information in several ways so that user can understand it very clearly. One thing I want to highlight here that user have flexibility to choose metal layers but out of available options. Stay tune to understand this point.

### Cross-section diagram of a Metal Stack:

First try to understand below pic :)

This is basically a cross-section of different metal wire after the fabrication. In the sense, how different metals are placed and how they are connected. Sometime lot more details can be provided along with this pictorial view like min_width and min_spacing of every metal wire, name of the dielectric, thickness of metal wire and dielectric. It varies from foundry to foundry & process to process.

Another representation of cross-section of Metal Stack (Source: VLSI Research INC - Downloaded from Internet)

Here you can see, they have explained from real fabrication point of view and also explained what are different components of first metal film stack, second metal film stack and so-on as per their process.

Note: Above cross-section foundry can provide for maximum available Metal stack. Now if you are confused what is the meaning of "available" metal stack (refer below pic)

### Tabular diagram of Metal Stack:

Basically it's metallization option available or say provided by the foundry. They can provide this in the table form to make things crystal clear. Cross-section diagram can help you but drawing the cross-section of each and every stack is not possible. So they created table something like this (below).

Note: I have only created a very small subset of actual table but it is sufficient to understand foundry data.

I have only captured 21 stack type. There can be more also. Now let's try to understand this table more closely.
• For 3 Metal layer - there is only 1 option available. (Stack type 1)
• For 4 Metal layer - there is only 1 option available. (Stack type 2)
• For 5 Metal layer - there is only 2 option available. (Stack type 3,4)
• For 6 Metal layer - there is only 3 option available. (Stack type 5,6,7)
• For 7 Metal layer - there is only 6 option available. (Stack type 8-13)
• For 8 Metal layer - there is only 8 option available. (Stack type 14-21)
• There are no other available options for any metal layer stack apart from provided in the table. Like if you need any other combinations of metals for 5 metal layer, it's not available. (Restriction provided by foundry)
• Metal layer "Mr" can not be used in case of 3, 4, 5 &6 metal layer stack. (Restriction provided by foundry)
• Top Metal layer can be of either Mz or Mr (for metal stack more then 6). (Restriction provided by foundry)
• My, Mx Layer can't be Top metal layer. These are always inter-layer metal. (Restriction provided by foundry)
• M1 is always First metal layer. (Restriction provided by foundry)
• Sequence of Metal layer is M1 -> Mx -> My -> Mz/Mr. You can't change the sequence. (Restriction provided by foundry)

Following information can supplement above diagram (also provided by foundry) and sometime easy to understand. If you can understand this properly, you can form any stack diagram or say you can understand all available options provided by foundry.

Similar type of table can be provided for VIA also.

Now from Foundry point of view, every things looks good. But you may be thinking
• How this information is going to use in the design?
• How are designers going to communicate with each other about a certain metal stack?
• Is there any standard for communication point of view with in a Design Team?
You may have lot of other questions, Lets wait for second part of this article to understand more about the Metal Layer Stacking from Designer point of view.

1. That's a good article. Actually, I was looking for this. I have certain questions.
1) You said restrictions provided by foundry. Is there any reasons for that?
2)Could you also please add some more points on passivation and bond openings?
3) What is the difference between Mz and Mr metals?
4) Do the different metals varies with min width and min spacing property alone or do they have different thickness?