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Sunday, December 31, 2017

Timing_sense : Timing Arc in .LIB Files (Part1)


Representation of The Unateness of timing Arc In timing Library:


In the Timing Library, "Timing Arc information" is stored with the syntax "timing_sense".

1) For Single Input and Single Output

Buffer : timing_sense: positive_unate

To know more about the Unateness of Buffer, please read Article "Unateness- Timing Arc: Buffer"
/* --------------- *
* Design : BUF2X1 *
* --------------- */
cell (buf){
   ....
   pin (A) {
      ....
       direction : input;
       capacitance : 1.0;
   } /* End pin (A) */

   pin(Y){
       direction : output;
       capacitance : 0.0;
       function : "(A)";
       ....
       ....
      timing(A_Y) {
          related_pin : "A";
          timing_sense : positive_unate;
           ....
           ....
      }
       ...
       ...
   }/* End pin (Y) */
}/* End cell (buf) */

So basically "timing_sense" will represent the unateness of a particular pin. But remember, if you wants to know the number of Timing Arc - then it's 2. One for Falling edge and other for Rising Edge.

Inverter : timing_sense: negative_unate

To know more about the Unateness of Inverter, please read Article "Unateness- Timing Arc: Inverter"
/* --------------- *
* Design : INVX1 *
* --------------- */
cell (inv){
   ....
   pin (A) {
      ....
       direction : input;
       capacitance : 1.0;
   } /* End pin (A) */

   pin(Y){
       direction : output;
       capacitance : 0.0;
       function : "(!A)";
       ....
       ....
      timing(A_Y) {
          related_pin : "A";
          timing_sense : negative_unate;
           ....
           ....
      }
       ...
       ...
   }/* End pin (Y) */
}/* End cell (inv) */

Note:
  • If you have noticed (or If you will compare in .lib file), through most of the parameters it's very difficult to understand whether it's Buffer or Inverter. There are only 2 parameter which can help you: "function" and "timing_sense".
  • Name inside the timing() - is the Timing Arc name.
  • You can see (in above examples) there is 1 Input Pin - which is A and one Output Pin which is Y. Now timing() is "related to" output Pin Y because timing arc is attached to an output pin. (you can get more clarity on this point later in this article)

2) For Multiple Input and Single Output

AND gate: timing_sense: positive_unate

To know more about the Unateness of AND gate, please read Article "Unateness- Timing Arc: AND gate"
/* --------------- *
* Design : AND2X1 *
* --------------- */
cell (AND2X1) {
       ....
       ....
      pin(A) {
            direction : input;
            capacitance : 0.01;
            rise_capacitance : 0.01;
            fall_capacitance : 0.01;
      }

      pin(B) {
            direction : input;
            capacitance : 0.01;
            rise_capacitance : 0.01;
            fall_capacitance : 0.01;
      }

      pin(Y) {
            direction : output;
            capacitance : 0;
            rise_capacitance : 0;
            fall_capacitance : 0;
            max_capacitance : 0.5;
            function : "(A B)";
            timing(A_Y) {
                  related_pin : "A";
                  timing_sense : positive_unate;
                  .....
                  .....
            }
            timing(B_Y) {
                  related_pin : "B";
                  timing_sense : positive_unate;
                  .....
                  .....
            }
            ....
            ....
      }
      .....
      .....
}

In this case both the Pins are of same type, we can combine the definition of timing arc into one. Like
  timing(A_Y, B_Y) {
    related_pin : "A B";
    timing_sense : negative_unate;
    ....
    ....
  }

Remember, all the parameters should be same. There are few parameters which we haven't discuss till now, but in reality before combining we have to review all.

OR gate: timing_sense: positive_unate

To know more about the Unateness of OR Gate, please read Article "Unateness- Timing Arc: OR Gate"
/* -------------- *
* Design : OR2X1 *
* -------------- */
cell (OR2X1) {
       ....
       ....
       pin(A) {
             direction : input;
             capacitance : 0.015;
             rise_capacitance : 0.015;
             fall_capacitance : 0.015;
       }
       pin(B) {
             direction : input;
             capacitance : 0.01;
             rise_capacitance : 0.01;
             fall_capacitance : 0.01;
       }
       pin(Y) {
             direction : output;
             capacitance : 0;
             rise_capacitance : 0;
             fall_capacitance : 0;
             max_capacitance : 0.4;
             function : "(A+B)";
             timing(A_Y) {
                   related_pin : "A";
                   timing_sense : positive_unate;
                   ....
                   ....
             }
             timing(B_Y) {
                   related_pin : "B";
                   timing_sense : positive_unate;
                   ....
                   ....
             }
       ....
       ....
       }
}

NOR gate: timing_sense: negative_unate

To know more about the Unateness of NOR gate, please read Article "Unateness- Timing Arc: NOR gate"
/* -------------- *
* Design : NOR2X1 *
* -------------- */
cell (NOR2X1) {
       ....
       ....
       pin(A) {
             direction : input;
             capacitance : 0.015;
             rise_capacitance : 0.015;
             fall_capacitance : 0.015;
       }
       pin(B) {
             direction : input;
             capacitance : 0.01;
             rise_capacitance : 0.01;
             fall_capacitance : 0.01;
       }
       pin(Y) {
             direction : output;
             capacitance : 0;
             rise_capacitance : 0;
             fall_capacitance : 0;
             max_capacitance : 0.4;
             function : "(!(A+B))";
             timing(A_Y) {
                   related_pin : "A";
                   timing_sense : negative_unate;
                   ....
                   ....
             }
             timing(B_Y) {
                   related_pin : "B";
                   timing_sense : negative_unate;
                   ....
                   ....
             }
       ....
       ....
       }
}

NAND gate: timing_sense: negative_unate

To know more about the Unateness of NAND gate, please read Article "Unateness- Timing Arc: NAND gate"
/* --------------- *
* Design : NAND2X1 *
* --------------- */
cell (NAND2X1) {
       ....
       ....
      pin(A) {
            direction : input;
            capacitance : 0.01;
            rise_capacitance : 0.01;
            fall_capacitance : 0.01;
      }

      pin(B) {
            direction : input;
            capacitance : 0.01;
            rise_capacitance : 0.01;
            fall_capacitance : 0.01;
      }

      pin(Y) {
            direction : output;
            capacitance : 0;
            rise_capacitance : 0;
            fall_capacitance : 0;
            max_capacitance : 0.5;
            function : "(!(A B))";
            timing(A_Y) {
                  related_pin : "A";
                  timing_sense : negative_unate;
                  .....
                  .....
            }
            timing(B_Y) {
                  related_pin : "B";
                  timing_sense : negative_unate;
                  .....
                  .....
            }
            ....
            ....
      }
      .....
      .....
}

XNOR gate: timing_sense: non_unate

To know more about the Unateness of XNOR gate, please read Article "Unateness- Timing Arc: XNOR gate"
/* -------------- *
* Design : XNOR2X1 *
* -------------- */
cell (XNOR2X1) {
       ....
       pin(A) {
             direction : input;
             ....;
       }
       pin(B) {
             direction : input;
             ....;
       }
       pin(Y) {
             direction : output;
             ....;
             function : "(!(A^B))";
             timing(A_Y) {
                   related_pin : "A";
                   timing_sense : non_unate;
                   ....
                   ....
             }
             timing(B_Y) {
                   related_pin : "B";
                   timing_sense : non_unate;
                   ....
                   ....
             }
       ....
       }
}

XOR gate: timing_sense: non_unate

To know more about the Unateness of XOR gate, please read Article "Unateness- Timing Arc: XOR gate"
/* -------------- *
* Design : XOR2X1 *
* -------------- */
cell (XOR2X1) {
       ....
       ....
       pin(A) {
             direction : input;
             ....;
       }
       pin(B) {
             direction : input;
             ....;
       }
       pin(Y) {
             direction : output;
             ....;
             function : "(A^B)";
             timing(A_Y) {
                   related_pin : "A";
                   timing_sense : non_unate;
                   ....
                   ....
             }
             timing(B_Y) {
                   related_pin : "B";
                   timing_sense : non_unate;
                   ....
                   ....
             }
       ....
       }
}

Representation of Unateness for few more complex circuits (like MUX) and Sequential circuits, we will discuss in next Articles.

Monday, December 25, 2017

Single VIA, VIA array, Stacked VIA


A via forms a connection between overlapping geometries on different layers through a cut layer, and is formed by geometries on all three layers.
Three types of vias:
  1. a single via,
  2. an array via,
  3. and a stacked via.

1) Single VIA



Below diagram help you to understand how single VIA are placed between 2 metal and help them to connect them.
2D /Top view with different arrangement (also known as Layout View)


3D view (Help you to understand connection more closely).

Figure 3D_b is a transparent view of the 3D_a. It helps you to understand how different layers are connected with each other.

Side View of Via and Metal connection.


There are certain Design rules for VIAs also. I am not going to capture those in detail here but below figure give you a general idea.


Vias can be asymmetric, meaning the overhangs in the x and y directions are different. The overhang parameters refer to those of a via connecting preferred-direction wires. If the wires are in the nonpreferred direction, the via is rotated and the overhangs are reversed, meaning that the extensions in the x direction are given by the y overhang parameters.

2) VIA Array



Array vias are used for connecting wide wires where the required cut size would exceed the maximum cut size of the simple via. In an array via, the region of intersection of the wires is filled by a regular array of small cuts of fixed size and separation.

2D /Top view with and without preferred direction of Metal arrangement (also known as Layout View)


3D view (Help you to understand connection more closely).


Figure 3D_b is a transparent view of the 3D_a. It helps you to understand how different layers are connected with each other. you can also see that array size is 3x1 between M1 and M2. When it comes to M2 and M3, Single VIA connects both the wire. But dnt think that it will always be the case. It depends on design that and width of Metal wire, if you want to use VIA array or Single VIA. In the below figure, you can see that M1 and M2 are using 3x3 VIA array. Between M2 and M3 - it's 1x3 VIA array.


3) Stack VIA



3D view (Help you to understand connection more closely).


2D view of Stack via is not easy to understand. But if you want to try, you can do it in any tool to understand properly.

I can summarize this article with combined view of all 3 type of VIAs.



Must Read Article

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