## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Sunday, December 31, 2017

### Timing_sense : Timing Arc in .LIB Files (Part1)

 STA & SI:: Chapter 1: Introduction 1.1a 1.1b 1.1c 1.2a 1.2b INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

### Representation of The Unateness of timing Arc In timing Library:

In the Timing Library, "Timing Arc information" is stored with the syntax "timing_sense".

1) For Single Input and Single Output

Buffer : timing_sense: positive_unate

/* --------------- *
* Design : BUF2X1 *
* --------------- */
cell (buf){
....
pin (A) {
....
direction : input;
capacitance : 1.0;
} /* End pin (A) */

pin(Y){
direction : output;
capacitance : 0.0;
function : "(A)";
....
....
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
....
....
}
...
...
}/* End pin (Y) */
}/* End cell (buf) */

So basically "timing_sense" will represent the unateness of a particular pin. But remember, if you wants to know the number of Timing Arc - then it's 2. One for Falling edge and other for Rising Edge.

Inverter : timing_sense: negative_unate

/* --------------- *
* Design : INVX1 *
* --------------- */
cell (inv){
....
pin (A) {
....
direction : input;
capacitance : 1.0;
} /* End pin (A) */

pin(Y){
direction : output;
capacitance : 0.0;
function : "(!A)";
....
....
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
....
}
...
...
}/* End pin (Y) */
}/* End cell (inv) */

Note:
• If you have noticed (or If you will compare in .lib file), through most of the parameters it's very difficult to understand whether it's Buffer or Inverter. There are only 2 parameter which can help you: "function" and "timing_sense".
• Name inside the timing() - is the Timing Arc name.
• You can see (in above examples) there is 1 Input Pin - which is A and one Output Pin which is Y. Now timing() is "related to" output Pin Y because timing arc is attached to an output pin. (you can get more clarity on this point later in this article)

2) For Multiple Input and Single Output

AND gate: timing_sense: positive_unate

To know more about the Unateness of AND gate, please read Article "Unateness- Timing Arc: AND gate"
/* --------------- *
* Design : AND2X1 *
* --------------- */
cell (AND2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.5;
function : "(A B)";
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
.....
.....
}
timing(B_Y) {
related_pin : "B";
timing_sense : positive_unate;
.....
.....
}
....
....
}
.....
.....
}

In this case both the Pins are of same type, we can combine the definition of timing arc into one. Like
timing(A_Y, B_Y) {
related_pin : "A B";
timing_sense : positive_unate;
....
....
}

Remember, all the parameters should be same. There are few parameters which we haven't discuss till now, but in reality before combining we have to review all.

OR gate: timing_sense: positive_unate

To know more about the Unateness of OR Gate, please read Article "Unateness- Timing Arc: OR Gate"
/* -------------- *
* Design : OR2X1 *
* -------------- */
cell (OR2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.015;
rise_capacitance : 0.015;
fall_capacitance : 0.015;
}
pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.4;
function : "(A+B)";
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : positive_unate;
....
....
}
....
....
}
}

NOR gate: timing_sense: negative_unate

To know more about the Unateness of NOR gate, please read Article "Unateness- Timing Arc: NOR gate"
/* -------------- *
* Design : NOR2X1 *
* -------------- */
cell (NOR2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.015;
rise_capacitance : 0.015;
fall_capacitance : 0.015;
}
pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.4;
function : "(!(A+B))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
....
}
....
....
}
}

NAND gate: timing_sense: negative_unate

To know more about the Unateness of NAND gate, please read Article "Unateness- Timing Arc: NAND gate"
/* --------------- *
* Design : NAND2X1 *
* --------------- */
cell (NAND2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.5;
function : "(!(A B))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
.....
.....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
.....
.....
}
....
....
}
.....
.....
}

XNOR gate: timing_sense: non_unate

To know more about the Unateness of XNOR gate, please read Article "Unateness- Timing Arc: XNOR gate"
/* -------------- *
* Design : XNOR2X1 *
* -------------- */
cell (XNOR2X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(!(A^B))";
timing(A_Y) {
related_pin : "A";
timing_sense : non_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : non_unate;
....
....
}
....
}
}

XOR gate: timing_sense: non_unate

To know more about the Unateness of XOR gate, please read Article "Unateness- Timing Arc: XOR gate"
/* -------------- *
* Design : XOR2X1 *
* -------------- */
cell (XOR2X1) {
....
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(A^B)";
timing(A_Y) {
related_pin : "A";
timing_sense : non_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : non_unate;
....
....
}
....
}
}

Representation of Unateness for few more complex circuits (like MUX) and Sequential circuits, we will discuss in next Articles.