VLSI BASICS:
- CMOS logic Basis
- Physical Design basics
- Hierarchical Design Flow
- Basic Flow
- Flow Benefits
- Setting Block Level Constraints
- Limitation in Hierarchical Design
Timing Analysis:
- Basic Of Timing Analysis In Physical Design.
- What is Timing Analysis
- Type Of Timing Analysis
- Static Timing Analysis
- Dynamic Timing Analysis
- Basic Of Timing Analysis.
- Clock Related
- Flip Flop Related
- Static Timing Analysis
- Timing Paths:
- Data path
- Clock path
- Clock Gating path
- Asynchronous Path
- Other paths
- Critical path
- False Path
- Multi-cycle path
- Single Cycle path
- Launch Path and Capture Path
- Longest Path ( also know as Worst Path , Late Path , Max Path , Maximum Delay Path )
- Shortest Path ( Also Know as Best Path , Early Path , Min Path, Minimum Delay Path)
- Time Borrowing
- Setup And Hold Time
- Setup And Hold Time For Multi-Cycle ( in progress)
- Setup And Hold Time For Latch Based Circuit (in progress)
- Delay
- Timing Path delay
- Major Classification of Delay
- Cell Delay
- Net Delay
- Parameters On Which Delay Depends
- Interconnect Delay Models
- Lumped Capacitor Model
- Lumped RC Model
- Distributed RC Model
- Pi RC Model
- T RC Model
- RLC Model
- Wire Load Model
- Elmore Delay Model
- Transmission Line Model
- SDF (Standard Delay Format/Synopsys Delay Format)
- Tool Using this format
- Information In SDF
- Requirement Of SDF
- SDF Constructs
- Syntax of SDF File
- Header Section
- Cell Section
- Static Timing Analysis Using EDA tools
- Type of Checking Performed
- Analysis Feature
- Different type of Data Format required For STA using EDA tools
- Design Netlist (*.dbs , Verilog, VHDL)
- Timing Libraries (*.dbs , *.libs , tlf)
- Delay Information (SDF)
- Parasitic Data (SPEF, SBEF, RSPF)
- Timing Constraints (SDC)
- STA Flow
- Pre-Layout Design
- Post-Layout Design
- Prime Time Sample Script
- Static Timing Analysis Flow (Prime-Time as a reference)
- Basics of Design Constraints.
- Classification or types of "Design Constraints".
- Design Rule Constraints
- Optimization Constraints
- Different type of "Design Rule Constraints".
- Maximum transition time
- Maximum fanout.
- Maximum (and minimum) capacitance.
- Cell degradation
- Synopsys Design Constraints (SDC)
- ILM (Interface Logic Models)
- ETM (Extracted Timing Models)
- QTM (Quick Timing Models)
- Phone Screen : Timing Based Interview Questions
Clock:
- CRP (Clock Reconvergence Pessimism)
- What is CRP?
- How to remove CRP?
Signal Integrity:
Parasitic Extractions.
- Parasitic Interconnect Corner
- Basic of Interconnects
- Capacitance Of Interconnect wire
- Resistance Of Interconnect Wire.
- Different Type of Parasitic Data format
- SPEF
- DSPF
- RSPF
- SPF
- SBPF
- Interview Questions / Frequently Asked Questions
- Antenna Effects
- What is antenna effects?
- Design Solution to reduce the antenna effect.
- Jumper instertion
- Diode insertion.
- Antenna Rules
- Caliber
- Magma
- Synopsys
- Conformal Dielectric
- Process Variation
- Type of Process variation
- Random Variation
- Systematic Variation
- Inter-die or Die-to-Die variation
- Intera-die or Within-Die Variation
- Modelling of Variation
the site is really very good.. gr8 job....
ReplyDeletecan u please write about metastability and frequency dividers....
Wonderful website and very helpful. Thanks to everybody involved in this, specially the lecturers, Thank you Sir:)
ReplyDeletereally grt work ... description is in really easy and understandable language waiting for more posts.... :)
ReplyDeleteVery exciting and helpful.. Thanks!
ReplyDeletegod bless u 4 this wonderful job
ReplyDeletegod may accomplice all ur desires
thanks :)
from where did u copy ???
ReplyDeletetell me book asap ghade :@
great articles!
ReplyDeleteIs there an option to download all articles as pdf files?
Not till now.
Deletesir ,
ReplyDeletewill you please add some of the cells in library like well tap , end cap , de cap ......... cells why they are used in the design and their internal structure . that will be very useful to us.
Sure -- I will try my best to do so.
DeleteExcellent and very useful site. congratulations for the team site.
ReplyDeletethanks man/women :)
DeleteHi Please upload a ASIC Physical Design (PD) Questions with answers that can be asked in Interviews.
ReplyDeleteRajesh
And If hold time is Th for a flip flop and if data is not stable **** Before ****8 Th time from active edge of the clock , there is a hold violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) after active clock edge, then it's a Hold violation.
ReplyDeleteMay God Bless you. Your blog has been of immense help.
ReplyDeletethank you very much..
ReplyDeletethank you very much. The information is very useful
ReplyDeletesir pls send me some usefull documents on chapter 7 few vlsi terminolgy .... at piyuw1791@gmail.com
ReplyDeletePlease correct the Verilog in both examples below. Explain in each example what the problem is.
ReplyDeleteExample 1
always @ (s1)
begin
if (s1)
output1=a + b;
else
output2=b + c;
end
Example 2
assign data2 = in2 ;
always @ (clock)
data2 <= in1
Hi Ramesh,
DeleteSomehow not able to understand your comment.
can u please expain the soc flow in one of your blog?
ReplyDeleteI am not getting time these days. Busy in office work. I will update soon.
DeleteAWESOME SIR
ReplyDeletePlease suggest hiring freshers VLSI companies.
thanks
Please start posts on scripting languages used in VLSI industry like Tcl, Perl, SKILL
ReplyDeleteyour site is a bible for vlsi
ReplyDeleteIf someone is using icc tool for first time for physical verification from where he can get information about basic commands like get_cell, get_objects.....etc
ReplyDeleteManual of the tools.. :)
DeleteFabulous work Sir...Great...
ReplyDeleteVery few people are there who really share knowledge for free...
Keep up the good work. Long Live!:)