tag:blogger.com,1999:blog-4597498589834570435.post6146666785567462098..comments2024-02-27T14:29:13.618+05:30Comments on VLSI Concepts: Maximum Clock Frequency : Static Timing Analysis (STA) basic (Part 5b)VLSI Experthttp://www.blogger.com/profile/01205530113106138349noreply@blogger.comBlogger86125tag:blogger.com,1999:blog-4597498589834570435.post-48582252858889769242021-11-07T16:49:25.319+05:302021-11-07T16:49:25.319+05:30you got the wrong idea of min time period hereyou got the wrong idea of min time period hereAnonymoushttps://www.blogger.com/profile/12732930263403630532noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-83229914585814322632021-11-07T16:47:28.315+05:302021-11-07T16:47:28.315+05:30SO in Example 4, we have also included reg2reg bec...SO in Example 4, we have also included reg2reg because we must make sure clock wont violate setup time?Anonymoushttps://www.blogger.com/profile/12732930263403630532noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-52805493393996786562021-07-24T10:53:32.247+05:302021-07-24T10:53:32.247+05:30Hi in example 5, why are we not considering the cl...Hi in example 5, why are we not considering the clock delay?<br />V.H.WEASLEYhttps://www.blogger.com/profile/09153861389007052906noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-26433758729583489582021-06-08T16:34:05.298+05:302021-06-08T16:34:05.298+05:30With very Same issue, I was also thinking about it...With very Same issue, I was also thinking about it. I think and I am not 100% sure but the idea is for Clock to out delay there is only one FF available(The one connected at the output). All the other FFs are connected to input of the FF connected at the output. The clk to Q delay of that is 2(buffer) + 5(clk-Q) + 6(buffer at output) = 13 ns. That is less then what we calculated. So, that is why.Anonymoushttps://www.blogger.com/profile/13704344173750590747noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-29283636476977836662021-05-26T03:36:47.520+05:302021-05-26T03:36:47.520+05:30hi , thanks for all the info . I have a problem st...hi , thanks for all the info . I have a problem statement in which we have to find the clock frequency <br /> circuit is connected as below <br />flopA-combinational delay(3units) - flopB - combination delay ( 4units) - flopC combination delay(5) - flopA<br />set up is 1 and clk2q delay is zero for all flops<br />so operating clock frequency will be 1/(5+1) = 1/6ns ( since flop c to flop A hasnavyasree matturuhttps://www.blogger.com/profile/15010728208554687125noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-42173482040508604712021-03-23T01:56:33.491+05:302021-03-23T01:56:33.491+05:30Sir in example 5 why we you are not considering cl...Sir in example 5 why we you are not considering clock_to_out delay while calculating max. frequency...while in example 4 we you have considered thatShubhamhttps://www.blogger.com/profile/17174925329554620884noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-90836701068614401842020-11-05T18:36:51.171+05:302020-11-05T18:36:51.171+05:30Sir why don't we consider the clock uncertaint...Sir why don't we consider the clock uncertainty and derate factors here?Tanhttps://www.blogger.com/profile/06330692392427161606noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-5347882113250073972020-09-01T03:43:41.785+05:302020-09-01T03:43:41.785+05:30Can someone please explain that why haven't we...Can someone please explain that why haven't we considered pin2pin delay in the last example?mohitmathur133https://www.blogger.com/profile/07759630200704952853noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-44247850767466753452020-05-03T17:58:21.385+05:302020-05-03T17:58:21.385+05:30In example 1, the minimum time is 11ns, but why is...In example 1, the minimum time is 11ns, but why is 16ns considered as minimum time as it is the maximum of all values? I am confused! Please help.Anonymoushttps://www.blogger.com/profile/05011233441437158673noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-6755166341478265122020-04-08T14:06:41.311+05:302020-04-08T14:06:41.311+05:30Hi expert, I am totally convinced with your explan...Hi expert, I am totally convinced with your explanation related to - why we are not considering input_pin-to-Register_delay in the calculation for clock frequency (in Example 4).<br />But, I still have 2 more doubts : <br />1. Why we are not considering the Register-to-Output_pin_delay to calculate the clock frequency?<br />2. Why in example 5 we have only considered the data paths for Anonymoushttps://www.blogger.com/profile/08053191634919467744noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-7591209232150832902019-10-05T19:50:52.771+05:302019-10-05T19:50:52.771+05:30sir why do we consider pin2pin delay while calcula...sir why do we consider pin2pin delay while calculating the maximum clock frequency ?<br />clock does not have any role to play in pin2pin delay containing only combitorial logic circuitAnonymoushttps://www.blogger.com/profile/09760950186275388854noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-60210214032485137752019-10-02T19:21:09.685+05:302019-10-02T19:21:09.685+05:30To calculate max freq, we have to consider 3 types...To calculate max freq, we have to consider 3 types of paths:i/p to o/p, reg to reg and clk port to output port.In example 5, there is no direct path from i/p to o/p, so it is not considered for max freq.Also there is only one path from clk port to output port with delay 2+5+6=13ns.This path should also be considered although it has not max delay.There are 7 reg to reg paths.So, among these 8 Anonymoushttps://www.blogger.com/profile/14342290003147772979noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-61738385479685003842019-09-18T15:29:22.929+05:302019-09-18T15:29:22.929+05:30hello sir, i really loved the way you have explain...hello sir, i really loved the way you have explained. but there was a concern that was bothering me from a long time.<br />Q: if we are calculating max time period from rise edge to fall edge and we are considering all the possible delays including tc2q and setup, then why don't we consider (add) hold time?sridevi tallurihttps://www.blogger.com/profile/06876203022355541058noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-70356444860758445812019-05-18T16:49:08.079+05:302019-05-18T16:49:08.079+05:30Sir in example 2
data path max delay= 2+11+2+...Sir in example 2 <br /> data path max delay= 2+11+2+9+2=26ns,we are adding the wire delay of clock of FF1 to data path instead of clock path.Is there any specific reason for that because I thought it was supposed to be added to the clock path?<br /> Anonymoushttps://www.blogger.com/profile/06854723917621133688noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-39679120622347049152018-10-04T15:31:12.935+05:302018-10-04T15:31:12.935+05:30Good explanations.
As in example 2, we can genera...Good explanations. <br />As in example 2, we can generalise, Min clock period = Max data path delay - Minimum clock path delay + Setup time.<br />In this case for example 5, why are the other data path delays not considered?Unknownhttps://www.blogger.com/profile/13626083926002626624noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-79898463863165240652018-08-05T09:07:54.132+05:302018-08-05T09:07:54.132+05:30hi sir,
first of all thanks for this awesome blog...hi sir, <br />first of all thanks for this awesome blog. i have a doubt regarding second question. why haven't u included 2ns delay of buffer in clock path in reg to reg delay? the registers cant be triggered unless clock is being applied to them.Parth khatterhttps://www.blogger.com/profile/10814777433468672659noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-56386797109672224722018-05-05T13:05:41.528+05:302018-05-05T13:05:41.528+05:30Hi
Sir
In example 4 when find register to regi...Hi <br /> Sir<br />In example 4 when find register to register delay then not consider setup time but same exaple in STA (3 C) problem 2 when find register to register delay then consider setup time.<br />plz explain sir<br />Thank you sir Anonymoushttps://www.blogger.com/profile/01880489737317809845noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-74153828350902807452018-05-05T12:58:31.823+05:302018-05-05T12:58:31.823+05:30Hi
Sir.
In example 4 when find register to regi...Hi<br /> Sir.<br />In example 4 when find register to register delay then not consider any hold time, but same example in portion STA(part 3 c) problem 2, when find register to register delay then consider hold time.<br />pls explane sir.<br />Thank you sir.Anonymoushttps://www.blogger.com/profile/01880489737317809845noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-37126536516589453742017-08-21T01:22:03.012+05:302017-08-21T01:22:03.012+05:30hello sir
thanq
I have gone through previous blog...hello sir <br />thanq<br />I have gone through previous blogs<br /><br />I have similar doubt that why we consider I/p to o/p because in the case similar, input to reg. would also be considered because input of U3 also depend on FF U2 o/p (depends on clock) so data must be stable at d for next clock. <br />that is I am confused weather to consider - input to register also (as asked above) and Anonymoushttps://www.blogger.com/profile/14288381070450670165noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-53125730152394677752017-08-20T08:42:51.380+05:302017-08-20T08:42:51.380+05:30In example 4 why we are not including setup time o...In example 4 why we are not including setup time of FF for calculation of data path from reg to reg and input pin to reg.Anonymoushttps://www.blogger.com/profile/15750728963824136756noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-16230746487466293372017-08-13T11:27:03.962+05:302017-08-13T11:27:03.962+05:30Your article is awesome! How long does it take to ...Your article is awesome! How long does it take to complete this article? I have read through other blogs, but they are cumbersome and confusing. I hope you continue to have such quality articles to share with everyone! I believe there will be many people who share my views when they read this article from you!<br /><a href="http://iogames-online.com" rel="nofollow">io games online</a><br />vexhttp://vex-3.comnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-86007519806608130802017-08-12T16:15:48.177+05:302017-08-12T16:15:48.177+05:30Your article is awesome! How long does it take to ...Your article is awesome! How long does it take to complete this article? I have read through other blogs, but they are cumbersome and confusing. I hope you continue to have such quality articles to share with everyone! I believe there will be many people who share my views when they read this article from you!<br /><a href="http://happywheels8.com" rel="nofollow">happy wheels</a><br />slither iohttp://slitherio-o.comnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-71973609085604485272017-08-11T16:05:57.836+05:302017-08-11T16:05:57.836+05:30Thanks for appreciating. Thanks for appreciating. VLSI Experthttps://www.blogger.com/profile/01205530113106138349noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-31056101322739963112017-08-11T15:49:29.564+05:302017-08-11T15:49:29.564+05:30Your article is detailed, thanks to it I solved th...Your article is detailed, thanks to it I solved the problem I am entangled. I will regularly follow your writers and visit this site daily.<br />wings iohttp://wingsio0.comnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-84240698584851354522017-07-07T01:08:24.264+05:302017-07-07T01:08:24.264+05:30in example 4 for calculating max freq we should fi...in example 4 for calculating max freq we should find out min clock period and that min clock period should not violate setup condition in any other flop of circuit<br /><br />in this example two paths are there b/w flops<br />1st U2to U1 Tclk>=16ns<br />2nd U1 to U2 Tclk>=15ns<br /><br />for max freq we should take min clock period(tclk >=15ns) but this will violate setup time Anonymoushttps://www.blogger.com/profile/12157799204595883155noreply@blogger.com