tag:blogger.com,1999:blog-4597498589834570435.post8556215832382366827..comments2024-02-27T14:29:13.618+05:30Comments on VLSI Concepts: Delay - "Interconnect Delay Models" : Static Timing Analysis (STA) basic (Part 4b)VLSI Experthttp://www.blogger.com/profile/01205530113106138349noreply@blogger.comBlogger15125tag:blogger.com,1999:blog-4597498589834570435.post-16964135799593601062018-05-24T00:38:18.406+05:302018-05-24T00:38:18.406+05:30Keep this going please, great job!Keep this going please, great job!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-62587756177973348082018-03-18T23:28:49.116+05:302018-03-18T23:28:49.116+05:30Sir,please tell me how to measure delay for a digi...Sir,please tell me how to measure delay for a digital circuit in transient analysis using synopsys hspice netlist.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-65919038746966471652018-03-18T08:38:12.929+05:302018-03-18T08:38:12.929+05:30Its like you read my mind! You seem to know so muc...Its like you read my mind! You seem to know so much about this, like you wrote the book in it or something.<br /><br />I think that you could do with a few pics to drive the message home <br />a little bit, but other than that, this is wonderful blog.<br />An excellent read. I will definitely be back.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-3617093383991081282017-08-07T08:07:50.154+05:302017-08-07T08:07:50.154+05:30Your article reflects the issue people are concern...Your article reflects the issue people are concerned about. The article provides timely information that reflects multi-dimensional views from multiple perspectives. I look forward to reading quality articles that contain timely information from you.html colorhttp://htmlcolorspicker.comnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-32660085889197229362016-08-16T12:59:27.839+05:302016-08-16T12:59:27.839+05:30While calculating the cell delays we consider the ...While calculating the cell delays we consider the loading effect of interconnect on the cells. Then we calculate the delays through the nets as well. Arn't we adding the delays of the interconnects twice,Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-81316633367437932002016-08-16T12:46:07.987+05:302016-08-16T12:46:07.987+05:30This is still not clear. Could you please explain ...This is still not clear. Could you please explain more on this.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-67115688574804736212016-08-16T12:43:58.501+05:302016-08-16T12:43:58.501+05:30This comment has been removed by the author.Anonymoushttps://www.blogger.com/profile/00380861203233200876noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-27612019511281506942015-04-20T10:04:20.607+05:302015-04-20T10:04:20.607+05:30Hi ... I am talking about the characteristics .. I...Hi ... I am talking about the characteristics .. It can be considered several time. we are not using the delay values twice.<br /><br />Think that you are traveling by a bus - you bus is not in a good condition - so you will feel tired after journey. So in case you have to visit somewhere - it matters how is your Bus condition. Means characteristic of BUS IMPACT a lot.<br />Since Bus is not in a VLSI Experthttps://www.blogger.com/profile/01205530113106138349noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-31999878203179321532015-03-06T17:23:33.072+05:302015-03-06T17:23:33.072+05:30Sir,
As u told we consider characteristics of Driv...Sir,<br />As u told we consider characteristics of Driver and load while calculating interconnect delay....but that is already consider in our cell delay....so it counts twice in delay calculationAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-19669610774468921542013-02-27T18:21:47.392+05:302013-02-27T18:21:47.392+05:30Dear Sir,
Please explain the need of interconnect ...Dear Sir,<br />Please explain the need of interconnect delay model.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-23373221333644956652012-03-07T14:30:50.786+05:302012-03-07T14:30:50.786+05:30Hi,
Its Done. Please Check the next blog.Hi,<br /><br />Its Done. Please Check the next blog.VLSI Experthttps://www.blogger.com/profile/01205530113106138349noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-73960949807198021532012-03-06T17:32:38.067+05:302012-03-06T17:32:38.067+05:30Dear sir,
please explain about wire load model als...Dear sir,<br />please explain about wire load model also.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-47057098105190311322012-03-06T00:19:34.398+05:302012-03-06T00:19:34.398+05:30excellent work for who are looking for detailed an...excellent work for who are looking for detailed and well explained STA especially fresherssharankumarnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-48788297638892293142011-09-19T08:57:57.416+05:302011-09-19T08:57:57.416+05:30Hi Shubham,
Its not like that .. we take care abou...Hi Shubham,<br />Its not like that .. we take care about the every reasons/cause of the delay with in a particular path. But we never do anything twice.If you can wait for sometime .. you will see in my few next blog, how we usually calculate the cell delay. Just give me some more time. If its urgent .. please drop me a mail.. I will try to explain you there..Your VLSInoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-19435816939666909422011-09-16T14:24:55.130+05:302011-09-16T14:24:55.130+05:30nice explanation.
I have a question though, when ...nice explanation. <br />I have a question though, when we calculate the total delay of the path we addup cell delay + interconnect delay and cell delay is calculated by taking into account the interconnect loading effect.So, isn't this wrong as we are taking the interconnect effect twice in our delay calculationShubhamnoreply@blogger.com