Tuesday, September 9, 2014

Creating Gate Oxide and Poly Layer: CMOS Processing (Part3)


Creating Gate Oxide and Poly Layer

Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different post based on below milestones.

Let’s start with the 3D diagram of silicon wafer where we left in the last post.
 
 

In the last post we have talked about the Field Oxide and here is Gate oxide. The gate oxide is the dielectric layer (silicon Oxide) similar to the Field Oxide but very thin in size. It separates the gate terminal of a MOSFET from the underlying source and drain terminals.
 
 
 
Final 3D diagram of silicon wafer.
 
 

Now we will deposit the polysilicon layer which will act as GATE contact. This Polysilicon layer also known as POLY in short.
 
 

Note:
Poly layer above the gate oxide is also known as GATE POLY and the poly above the Field Oxide also known as FIELD POLY. In other word, you can say that POLY with in the active region is known as GATE POLY because it helps in forming the Gate of Device and POLY outside the active region is known as FIELD POLY.

Final 3D Diagram of Silicon Wafer :


 
Till now we have created
  • Nwell
  • Active Region
  • Channel Stop Region
  • Field Oxide.
  • Gate Oxide
  • Poly layer.
In the next post we will talk about adding N+ impurities which will help us to create NMOS devices.
 
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