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Sunday, February 12, 2012

Parasitic Interconnect Corner (RC Corner) Basics - Part 1

BASICS OF CAPACITANCE AND RESISTANCE

(From VLSI design Point of View)

In the current technology, interconnects are playing a very important role. Today's topic of discussion is interconnect parasitic (Resistance and Capacitance) corners. My aim is to explain the below mention questions/concerns at the end of this series of blog.
  • What are these corners?
  • How Resistance and capacitance plays their role in deciding the corners?
  • How the complexity of these corners increases day by day?
  • For signoff the design (closing the timing and all) how many parasitic corners are required?
  • Is these corners has any dependency on the technology and if yes then how?
  • What are the use of these corners in STA and design cycle?
Now let’s start with few of the basics ( in case you need any details of any topic please let me know, I will try to capture of the details in next blog).
  • Metal layers are labeled according to the order in which they have fabricated, from the lower level 1 (meatl1) to the upper level (metal 6 in 0.12um). 
  • Maximum Number of metal layers, which any one can used in their design depends on the technology. Usually for this we use the terminology “Metal layer Stack”.
  • Each metal layer is connected (electrically) with the help of VIAs.
  • Between the 2 metal layers, there is a material know as Dielectric.  (please refer the below diagram for more understanding).

  • All the metal layers as per the technology has to follow certain design rules. 2 most important design rules  are
    • minimum width of metal layer and
    • minimum spacing  between the 2 metal layers.
  • These dimensions are critical and below this (value), there is a probability of manufacturing error rises to an unacceptable level (like shorts or opens). Please refer the below figure.

  • So prior fabrication, design rules must be checked  to ensure that the whole circuits complies with these rules. This process is known as DRC (Design Rule Check). (There are lot of other reasons for manufacturing error but right now it’s out of scope of this particular blog J ).
  • The width , spacing and thickness of metal layers vary as per the technology on which you are working. As you go down in the technology, these dimensions decreases continuously. You can get an rough idea from the following table.

Technology
Width (μm)
Thickness (μm)
Distance(space) (μm)
0.8μm
1.20
0.70
1.20
0.6μm
0.90
0.70
0.90
0.35μm
0.60
0.70
0.60
0.25μm
0.38
0.60
0.50
0.18μm
0.30
0.50
0.40
0.12μm
0.18
0.40
0.24
90nm
0.15
0.35
0.20
65nm
0.10
0.30
0.14


Note: These numbers may not be 100% correct. These can change as per the Foundry and the Metal layers also. Intention here is to provide an idea about the dimension with respect to the technology.

I think this much basic are more than sufficient. Now let’s build some story on the top of these basics. J

Interconnects lines form 2 important device in CMOS circuits: Resistance and Capacitance. Lets discuss these 2 in detail. It's very important that you should know these because these are going to help during the explanation of RC corners.

Capacitance of Interconnect wire:
  • Interconnect wires can store charges.  This is because all the interconnect wires are routed very close to each other. So when a signal travels through a wire then it (wire) behaves  like a plate having lot of charge. Now there may be 3 scenario:
    • Nearby wire or say plate also have some amount of charge (develop due to some signal flowing through that).
    • Or it has no signal -- acts like ground (Zero charge). 
    • Or it has same signal flowing at the same time (means similar type of charge at the same time).
  • As per the combination, there may or may not be a Capacitance. But last scenario (presence of same strength of signal at the same time) is a rare case. So in short we can say that most of the time there is a capacitance between 2 wires (interconnect).
Capacitance in the interconnect are classified as per the two wires/conductors/plates interacted with each other.  See the explanation..



As per the Diagram you can figure out that there are basically 3 types of capacitance.
1.       Coupling capacitance.
2.       Area Capacitance or Surface Capacitance.
3.       Fringe Capacitance.
Note: These name are some time different in different Foundry but most of the time we are using the above one.

Now for Structure A:
Cc : Coupling Capacitance between  central wire and its neighboring wire.
Ca : Area capacitance between  central wire and infinite bottom ground surface/wire/plate.
Cf : Fringe capacitance per side between central wire and infinite bottom ground surface/wire/plate.

So
Cbottom= Ca + 2Cf
Csum = Ca + 2Cf + 2Cc
Ctotal : Total Capacitance of the central wire.

For Structure B:
Cc   : Coupling Capacitance between  middle central wire and its neighboring wire.
Cat  : Area capacitance between  middle central wire and infinite top ground surface/wire/plate.
Cab : Area capacitance between  middle central wire and infinite bottom ground surface/wire/plate.
Cft : Fringe capacitance per side between middle central wire and infinite top ground surface/wire/plate.
Cfb : Fringe capacitance per side between middle central wire and infinite bottom ground surface/wire/plate.

So
Ctop = Cat + 2Cft
Cbottom= Cab + 2Cfb
Csum = (Cat + 2Cft) + (Cab + 2Cfb) + 2Cc
Ctotal : Total Capacitance of the middle central wire.

Now let’s talk about few formulas…

Surface Capacitance (Ca) per unit length= ε*(width of Metal)/(thickness of Dielectric)
                                                                  = ε*W/H
Coupling capacitance (Cc) per unit length = ε*(thickness of Metal)/(spacing between Metal wires)
                                                                    = ε*T/S
Below figure can give a more clear picture. where W and T represent the lateral width and the vertical thickness of an interconnect. The spacing between adjacent interconnects on the same layer is given by S and the inter-layer dielectric (ILD) thickness is given by H.



So you can figure out that the value of Capacitance has the dependency on
1.       Dielectric constant (ε)
2.       Width of Metal (W)
3.       Thickness of Metal (T)
4.       Spacing between the Metals (S)
5.       Thickness of Dielectric (ILD-Interlayer Dielectric) (H)

As you go down the technology, above mention parameters decreases (please refer the above table) and as per that capacitance increases or decreases.
  • W ↓    →   Ca ↓
  • S  ↓     →   Cc ↑
  • T  ↓     →   Cc ↓
  • But the rate by which the thickness of Metal is decreases in compare to the Space between the metal is less, so down the technology , effectively coupling capacitance is increases.
  • Down the technology, Area Capacitance is decreases.

That’s the one of the reason that in higher technology , designer ignore the coupling capacitance but in lower technology – coupling capacitance start playing an important role. And that’s why now a day everyone is more concern about  Crosstalk /Signal Integrity ( Which are the side effect of coupling capacitance).

Designers/VLSI Engineers always try to decrease the coupling capacitance as much as possible. They always come up with different-different idea. One of them is using different dielectric material with a low permittivity (this parameter is called LowK dielectric) between the gaps of interconnect.  This is the efficient technique to reduce the crosstalk capacitance while keeping the upper and lower capacitance almost unchanged. Low K dielectric were introduced with 0.18 μm technology. Air gap are the ultimate low K material, with a lowest possible K=1. Research is going on over this right now.



Resistance Of interconnect Wire:
Every material is associated with the property of resistivity. Conductors have very low resistivity, semiconductor material ( highly doped Silicon)  have moderate resistivity and Insulator have very high. We use different type of materials in CMOS circuit. Below table will provide a basic overview.

Type of material
Material used For
Resistivity at 25degC
(in Ω*cm)
Copper
Signal wire
1.72*E-6
Aluminum
Signal Wire
2.77*E-6
Gold
Bonding wire (chip and package)
2.20*E-6
Tungsten
Contacts
5.30*E-6
Highly doped Silicon
N+ diffusion
0.25 ( average- depends of level of doping)
Lightly doped Silicon
n-well
50


Note: There are several other materials also but above one are most common.

Formula for Resistance is very simple
Resistance per unit length = ρ/(width of metal)*(thickness of metal)
                                           = ρ/W*T
Where ρ is the resistivity of the metal.

As you go down the technology, above mention parameters decreases (please refer the above table) and as per that Resistance increases.
·         W ↓ → R ↑
·         T   ↓ → R ↑

Designers/VLSI Engineers always try to decrease the resistance by several mean. Because delay in the signal is directly proportional to the Resistance. And if delay is high then it’s almost impossible to design a high speed chip (high speed mean- delay should be very less). To reduce the resistance, designers/VLSI engineers took a major step when they move to 0.18μm technology.  Before that, material used for interconnect wire (signal wire) was Aluminum but now its Copper. From the above table, it’s clear that resistivity of Copper is almost 2 times lower than the Aluminum.

Resistivity of a material is usually consider as a constant value which is a very bad consideration. In the above table also I have mention the resistivity at 25degC. It mean it will change as per the temperature. The electrical resistivity of most materials changes with temperature. If the temperature T does not vary too much, a linear approximation is typically used:
ρ(T) = ρ0[1 + α(TT0)]
where α is called the temperature coefficient of resistivity, T0 is a fixed reference temperature (usually room temperature), and ρ0 is the resistivity at temperature T0.

You can read in few of the books that In general, resistivity of intrinsic semiconductors decreases with increasing temperature. The electrons are bumped to the conduction energy band by thermal energy, where they flow freely and in doing so leave behind holes in the valence band which also flow freely. The electric resistance of a typical intrinsic (non doped) semiconductor decreases exponentially with the temperature:

ρ(T) =ρ0*E(-αT)

But point to be noted that here we are talking about Interconnects/Wire and those are made of either Aluminum and copper (both are metals/conductor). So for interconnects –
·         Temp            ↑  → R ↑
·         Width           ↓  → R ↑
·         Thickness    ↓   → R ↑


 After Reading this part, Now I hope you have basic understanding about the Resistance and Capacitance with in the CMOS circuit's interconnects. Their dependence on the Width/thickness of Metals, Space between the Metals and thickness of Dielectric constant.

In the Next part we will discuss about the RC corners ( This blog's basic will help you there a lot)

12 comments:

  1. The blog was really good..
    Can you please update about RC Corners..
    Thanks.

    ReplyDelete
  2. Can you please update about RC Corners..

    ReplyDelete
  3. Sir, It was very informative description about parasitic. I am really curious about RC corners. How we comes on RCworst, RCbest etc..?? Waiting since last year. Please update soon.

    ReplyDelete
  4. Hi Sir,
    Thanks for the useful info .... I have doubt regarding metal layer stack .
    There are terms related to metal connections like open net , open locators and floating net ...Can u please explain how these will differ ?

    ReplyDelete
  5. This comment has been removed by the author.

    ReplyDelete
  6. This comment has been removed by the author.

    ReplyDelete
  7. The explanation is clear. Thanks!

    ReplyDelete
  8. The explanation is very clear, but i am still not clear about the difference between corners: Cbest, Cworst...versus RC extraction types in tools such as StarRC for example RC, C

    ReplyDelete

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