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Monday, July 20, 2015

Importance of CMP process

CMP (Chemical Mechanical Planarization) (Part 2)

(Importance of CMP process)

Chapter 3: Manufacturing Effects and Their Modeling
3.1 3.2a 3.2b 3.3a 3.3b 3.3c 3.4
Introduction Effect Of Etching Process Effect Of Etching Process Chemical Mechanical Planarization Importance Of CMP process Dishing & Erosion (CMP effects) Lithography
3.5a 3.5b 3.5c 3.5d 3.5e 3.5f 3.5g
Metal Width Variation (Type:1-2) Metal Width Variation (Type3) Metal Width Variation (Type:4-5) Metal Width Variation (Type6) Metal Width Variation (Type7) Metal Width Variation (Type8) Metal Width Variation (Summary)

In the last post we have discussed about the CMP process and very briefly raised the point of CMP side Effects (Dishing and Erosion).
Copper dishing and SiO2 erosion are undesirable because they reduce the final thickness of the copper line and leads to non-planarity of the surface resulting in complications when adding multiple levels of metal. Right now, if you are searching for definition then you have to wait. Right now I can only help you with below figure (which has some pictorial definition of these 2 effects).

You may have now 2 type of questions:
  • Why and how these issues (Erosion and Dishing) leads to non-planarity when adding multiple levels of metal.
  • Without CMP, there were also some non-planarity (I have mentioned that previously) and CMP supposed to remove that. But Now I am again talking about the Non-planarity. Then what’s the difference in both type of non-planarity.
Let me try to answer both of your questions in this Article.

First point can be understand by following figures along with their description.(Sometime Figures explain a lot compare to Description).

2D Ideal view:
Basically here I have tried to explain that if there is no issue,
  • All plates of Metal1 will start from a same reference level(or say height with respect to “0”/”zero” height of wafer). They will be coplanar.
  • Thickness of all plates of Metal1 is same.
  • Thickness of Dielectric1 should be same throughout the design.
  • All plates of Metal2 will start from a same reference level (or say height with respect to “0”/”zero” height of wafer). They will be coplanar.
  • Thickness of all plates of Metal2 is same.
  • Thickness of Dielectric2 should be same throughout the design.
  • Starting point of Dielectric2 is just above the Dielectric 1 and it will be in a straight line.

Note: You can’t see any irregularity (non-uniformity in Metal layer and Dielectric Loss) neither in Metal layers nor in Dielectric layers.

Because of CMP: 2D view:
Everything is changed. Irregularities (non-uniformity in Metal layer and Dielectric Loss) get introduced. There is a height and thickness variation.
  • Metal 1 starting level is same (because we have assumed that below that everything is ideal :).
  • Because of Dishing (Introduced as a side effect of CMP), Metal 1 thickness is changed.
  • Because of Erosion (Introduced as a side effect of CMP), Dielectric1 Thickness also changed.
    • More effected where Metal plates are present and less effected as we move away from the metal plates.
  • Since you will deposit Dielectric2 later on (After the CMP process is done for Metal1 and Dielectric1), so starting level of Dielectric2 will be as per top-level of Metal1 and Dielectric1.
    • In the below figure, you can notice that region2 was for Dielectric1 but after Dishing and Erosion, it become part of Dielectric2.
  • Now when you will deposit Metal2 on such surface, starting level of Metal2 automatically shifted (because it has dependency on the Top level of Dielectric1 (which is effected by Erosion).
  • After CMP on Metal2 and Dielectric2 structure leveling again distorted and dishing and Erosion will again take place.
  • Region4, which is originally assigned to Dielectric2 now will be part of Dielectric3.
In short I can say that:
  • Non-uniform copper and dielectric loss on M1 compounds the losses on M2 and higher metal levels.
  • CMP effects are cumulative
  • Multilevel effects impacts DOF (depth of focus), etch, and ultimately yield.

Note: These irregularity in the above figure is zoomed for your understanding but actually it’s far far better than the irregularity introduced when you will not do the CMP.  The reason I made this statement so that you don’t ask me that before and after there are irregularities, so why do CMP?  I have also explained this later.

Note: There are few recommended solution which can mitigate the effect of CMP like dummy filling and pillars/holes put in large width interconnects. I will discuss those later (this statement is going to support above Note and if same question came into your mind).

Same thing I have tried to cover into the 3D view. It may not be as accurate but you can understand what I am trying to convey.
  • Ideally:
    • Same metal thickness with certain level of leveling (from starting and ending point of view)
    • Constant Dielectric thickness and leveling across the wafer.
  • But after CMP:
    • Thickness of Metal layer changes
    • Dielectric leveling changes (Dielectric thickness Changes).
    • CMP effect Cumulates and affects other metal and Dielectric layers.

To justify my comment which I have made above that irregularity introduced by CMP is not same as before CMP, I have drawn few figure (tried my best) … (ufff few more figures).
After seeing the below figures, I am sure you can easily understand the differences and the importance of CMP. Best part is there are ways to minimize the side effect of CMP (Erosion and Dishing issue) with the help of few best practices + few other methods.

For higher nodes (like 90nm and above) these manufacturing issues are captured using the certain values based on width, spacing, density, thickness directly (also known as rule based approach via lookup tables or in the form of polynomial equations). These are present in the technology file used by extraction tool. Just an fyi that technology files are process dependent and created based on the information provided by the foundries like ICT and ITF file (We will discuss about these files later).

For lower nodes (below 90nm), due to the complexity of the process (multi-level effect) and dependency on lot of parameters (pressure, temperature, speed, pad material, slurry material etc.) it’s very difficult to exact model these variation using rule based approach.
Complexity of CMP process can be easily understandable by the following slide (captured from Internet).

Foundry and other partners develop a simulation based approach in which they take account of different effects, physical (Pad property, pressure, polish time, etc.) as well as chemical effects (slurry type, remover rate, etc.), and simulates the physical CMP process. In this approach as per the process and the design different hotspots are usually identify and accordingly corrective methods are applied. This approach is more accurate in comparison to rule based because
  • It’s not generic. It’s design dependent.
  • Different process parameters are considered and their effects are evaluated on the design. If any particular parameter can be neglected (on the basis of result), we can ignore that part also.
  • In rule based, to cover all sort of design a lot of pessimism has to be added, which can be ignored here (because it’s design dependent). It reduce pessimistic design guard band through more accurate timing/power analysis.
  • CMP model based approach also helps dummy fill optimization as compared to current rule (density) based approach (same reason as in above point – In the rule based, we have to add extra pessimism)
Note: RC Extraction can also use these “Data” for more accurate calculation of R and C. There are few Tools available in the market (like CCP – Cadence CMP Predictor, Prime-Yield).

In the next part, we will discuss about the Erosion and Dishing in detail.

Sunday, July 19, 2015

CMP (Chemical Mechanical Planarization) (Part 1: Introduction)

Introduction to CMP (Chemical Mechanical Planarization)

Chapter 3: Manufacturing Effects and Their Modeling
3.1 3.2a 3.2b 3.3a 3.3b 3.3c 3.4
Introduction Effect Of Etching Process Effect Of Etching Process Chemical Mechanical Planarization Importance Of CMP process Dishing & Erosion (CMP effects) Lithography
3.5a 3.5b 3.5c 3.5d 3.5e 3.5f 3.5g
Metal Width Variation (Type:1-2) Metal Width Variation (Type3) Metal Width Variation (Type:4-5) Metal Width Variation (Type6) Metal Width Variation (Type7) Metal Width Variation (Type8) Metal Width Variation (Summary)

Let’s first try to remind you the summary of very first article of this series. Below diagram can help you.

We are trying to study different manufacturing Effects which directly or indirectly effects Parasitic (RC) Extraction. CMP (Chemical Mechanical Planarization) is one of the important step from fabrication point of view and it play an important role in adding defects in the manufactured chip.

It’s a process of smoothing and planning the surfaces with the combination of chemical and mechanical forces. This process is a hybrid process of Chemical etching and free abrasive polishing. Individually,
  • Chemical etching cannot do planarization because of chemical reaction is isotropic in nature (For reference, you can refer ETCHING articles).
  • Similarly, Mechanical grinding for planarization alone is not sufficient (Theoretically it looks like it’s possible but practically a lot of challenges come). The chances of Surface damage is high in case of only mechanical grinding.
CMP has many advantages over standard “Reactive Ion Etching” (RIE) processes.
  • RIE processes cannot readily etch copper. CMP does a very good job removing copper.
  • In case of RIE process it’s difficult to etch the SiO2 and other dielectric layer smoothly. While CMP is mainly used for silicon dioxide, polysilicon, copper,low-κ dielectrics, and tungsten removal and planarization for the semiconductor wafer surface while at the same time producing a surface that is both very smooth and flat.
In CMP, as I have mentioned that it’s a hybrid process, it’s first calculate the degree of irregularities in the wafer and then make sure that high points on the wafer would be subjected to higher pressures from the pad as compared to lower points, hence, enhancing the removal rates there and achieving planarization.
You may not understand properly but may be below figure can help you in that.

In the above figure, assume that “a” is the intermediate stage of wafer (after few fabrication step) and now we have to add/deposit the “Copper Metal” for creating the Metal wires. Ideally, you are expecting something similar to “b” (Even I have explained the same in one of my previous article in the similar fashion). But point to be noted – I have used the word “Ideally”.  . Practically, it’s different – It will be something similar to “c”. Not plane surface at the top. You can’t use the same for next step because of these irregularities in the Metal layer. That’s why planarization is required and as I have explained above, CMP is the process of doing this. 

CMP is an elegant process and can be completed in a semiclean environment in the wafer fab. For understanding the process (how it perform actually in the Fabrication lab), you can watch below video.

Just try to explain also with the help of above diagram. Where you can see how polishing pad is used for planarization of wafer. Polishing table and Wafer Carrier usually rotate in different direction (at least at different axis), so rubbing action is sure. Rest details, I am sure you can figure out through the video.

For more understanding the importance of this, again refer the below figure.

Figure “a” is the wafer condition just before the Metal layer Deposition. Ideally after deposition, you need something similar to fig “b” but practically it’s difficult to fill only the “white spaces”, so in general you drop the metal completely which will automatically fill the “White Spaces” along with spreading in rest of the area also. Like in figure “c”. That’s the reason we need CMP process to remove the unwanted Metal (which also spread over the wafer) and creating shorts across all metal layers. As I am saying creating a shorts – so you can understand how important to do this precisely (means to ensure complete copper removal across the entire wafer).

More clear view in 3D

Remember with the help of CMP – we want to move from “c” to “b” or say achieve “b” structure from “c”.
Now it’s time to ask few questions from you –
  • Is it possible to get exact as we need after CMP process or not?
  • Is there any Disadvantage or say side effect of this process.
  • If yes, what are those? And how they impact the overall functionality.
Answer of all the questions are based on thing. There is nothing in this world without any side effect.  
CMP process has several potential defects (Side Effect) including
  • Stress cracking,
  • Delaminating at weak interfaces, and
  • Corrosive attacks from slurry chemicals.
These are due to the several process factors which play an important role in the CMP like Pressure, velocity, slurry composition.
During the CMP process, friction easily changes the temperature (near about 10degree increase compare to surrounding temperature). As the temperature rises, removal rate also increases (because of several reason – like chemical reaction act differently in high temp, softness also changes with high temperature).

Copper Dishing and SiO2 Erosion are 2 main surface defect which are result during the over-polishing step (which is required to ensure complete copper removal across the entire wafer) of CMP process. We will discuss these things in detail in next Article.

Friday, July 17, 2015

Effects of Etching Process (part2)

Effects Of Etching Process
(Few Terminology and Effect in the Thickness variation)

Chapter 3: Manufacturing Effects and Their Modeling
3.1 3.2a 3.2b 3.3a 3.3b 3.3c 3.4
Introduction Effect Of Etching Process Effect Of Etching Process Chemical Mechanical Planarization Importance Of CMP process Dishing & Erosion (CMP effects) Lithography
3.5a 3.5b 3.5c 3.5d 3.5e 3.5f 3.5g
Metal Width Variation (Type:1-2) Metal Width Variation (Type3) Metal Width Variation (Type:4-5) Metal Width Variation (Type6) Metal Width Variation (Type7) Metal Width Variation (Type8) Metal Width Variation (Summary)

In the previous post we have discussed the etching process and its main effect. If you remember then you can yourself figure out that those effects contribute in the width variation. Similarly there is another effect of Etching which contribute in the thickness of the layer. In this post I will discuss about that.

To understand this I will discuss few of the terminology related to etching. Few are going to help me in my story building (Means while I will explain the concept – how etching effects thickness), while few are for you info. 
Terminology used in Etching Process:
  • Etch Rate
  • Selectivity
  • Anisotropy
  • Uniformity
  • Etch Profile
  • Loading effect
  • Over etch
  • Residue

Let me try to provide one line definition…

Etch rate is a measure of how fast material is removed in the etch process.
Etch rate = (Thickness before etch - Thickness after etch)/Etch time
Etch rate depends on:
  • Gas flow / gas composition
  • Pressure
  • Source power
  • Bias voltage
  • Wafer temperature

Selectivity is a ratio of the etch rates between the different materials, especially the material that needs to be etched with respect to the material that we do not want to remove.

Where: S->; Infinity if ER1 >> ER2
ER is dielectric Constant.


The etching should be uniform within the wafer, from wafer-to wafer, from tool-to-tool. The uniformity is measured with wafer thickness by measuring the thickness at certain points before and after the etch process, and calculating the etch rates at these points.

(Max Etch rate – Min Etch rate)/(Max Etch Rate + Min Etch rate)

Etch Profile:

One of the most important characteristics of etch is the etch profile, which affects the next deposition processes. The profile is grouped into isotropic, anisotropic etch, and in between. Regarding these we have already discussed in the previous post.

Loading effect:

When the etch rate is dependent upon the amount of etchable surface exposed to the etchant, the phenomenon is called a Loading effect.

There are 2 type of loading effects (Note: below figures are copied from the Internet – not original version)
  • Macro Loading effect
    • In the Constant supply of Reactants, Etch rate goes down with increase the Surface Area

  • Micro Loading effect
    • For contact and via hole etch processes, the smaller hole has a lower etch rate than the larger holes because it is more difficult for the etchants to pass through the smaller hole, and etch by products are harder to diffuse out. Micro loading effect can be decreased by the low pressure process because the mean free path is longer.

Note: “Loading Effect” effects the thickness of the layer. Above few figure demonstrate this very well.

Over Etch:

When we do the etching, sometime (or I should say most of the time) unwanted material etched during the process. Like in the below example, we don’t want to etch Substrate but while etching FILM, some part of the substrate also etched. This is known as “Over Etch”.
(Below Figure is copied from the Internet)

Note: “Over Etch” effects the thickness of the layer. Above figure try to show the same.


Residue is reverse of the “over etch”. It usually happen as the corners. In short we want to remove the Film but because of corners/shapes, etch process don’t able to remove the Film completely.
(Below Figure is copied from the Internet)

When I have discussed a lot about the ETCH, let me give you some introduction of 2 different etching process here also (next article will be more focused on Manufacturing variation).
  • Positive Resist Etching Process
    • Positive photoresists develop at the exposed areas, while the unexposed resist remains on the substrate after development.
  • Negative Resist Etching Process.
    Negative photoresists behave opposite: The areas exposed crosslink during a subsequent baking step (post exposure bake, PEB) and remain after development.

    Note: “Residue” effects the thickness of the layer. Above explanation try to prove this.

    Last 3 (Loading effect, Residue, Over etch) are root cause of the thickness variation of layers.

    So before I close the ETCH process, let me summarize the concepts from manufacturing variation point of view.

    Because of different etch process (which we have discussed in this post and last post), the actual shapes may be any of the above. (Blue is what we need ideally and brown is what we will get actually/practically). If you have gone through above post seriously– you can easily figure out the reason of these (else message me).

    Let’s discuss few other fabrication related concepts in next few articles before we talk about the modeling of different type of variations.

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