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Monday, July 20, 2015

Importance of CMP process

CMP (Chemical Mechanical Planarization) (Part 2)

(Importance of CMP process)

Chapter 3: Manufacturing Effects and Their Modeling
3.1 3.2a 3.2b 3.3a 3.3b 3.3c 3.4
Introduction Effect Of Etching Process Effect Of Etching Process Chemical Mechanical Planarization Importance Of CMP process Dishing & Erosion (CMP effects) Lithography
3.5a 3.5b 3.5c 3.5d 3.5e 3.5f 3.5g
Metal Width Variation (Type:1-2) Metal Width Variation (Type3) Metal Width Variation (Type:4-5) Metal Width Variation (Type6) Metal Width Variation (Type7) Metal Width Variation (Type8) Metal Width Variation (Summary)

In the last post we have discussed about the CMP process and very briefly raised the point of CMP side Effects (Dishing and Erosion).
Copper dishing and SiO2 erosion are undesirable because they reduce the final thickness of the copper line and leads to non-planarity of the surface resulting in complications when adding multiple levels of metal. Right now, if you are searching for definition then you have to wait. Right now I can only help you with below figure (which has some pictorial definition of these 2 effects).

You may have now 2 type of questions:
  • Why and how these issues (Erosion and Dishing) leads to non-planarity when adding multiple levels of metal.
  • Without CMP, there were also some non-planarity (I have mentioned that previously) and CMP supposed to remove that. But Now I am again talking about the Non-planarity. Then what’s the difference in both type of non-planarity.
Let me try to answer both of your questions in this Article.

First point can be understand by following figures along with their description.(Sometime Figures explain a lot compare to Description).

2D Ideal view:
Basically here I have tried to explain that if there is no issue,
  • All plates of Metal1 will start from a same reference level(or say height with respect to “0”/”zero” height of wafer). They will be coplanar.
  • Thickness of all plates of Metal1 is same.
  • Thickness of Dielectric1 should be same throughout the design.
  • All plates of Metal2 will start from a same reference level (or say height with respect to “0”/”zero” height of wafer). They will be coplanar.
  • Thickness of all plates of Metal2 is same.
  • Thickness of Dielectric2 should be same throughout the design.
  • Starting point of Dielectric2 is just above the Dielectric 1 and it will be in a straight line.

Note: You can’t see any irregularity (non-uniformity in Metal layer and Dielectric Loss) neither in Metal layers nor in Dielectric layers.

Because of CMP: 2D view:
Everything is changed. Irregularities (non-uniformity in Metal layer and Dielectric Loss) get introduced. There is a height and thickness variation.
  • Metal 1 starting level is same (because we have assumed that below that everything is ideal :).
  • Because of Dishing (Introduced as a side effect of CMP), Metal 1 thickness is changed.
  • Because of Erosion (Introduced as a side effect of CMP), Dielectric1 Thickness also changed.
    • More effected where Metal plates are present and less effected as we move away from the metal plates.
  • Since you will deposit Dielectric2 later on (After the CMP process is done for Metal1 and Dielectric1), so starting level of Dielectric2 will be as per top-level of Metal1 and Dielectric1.
    • In the below figure, you can notice that region2 was for Dielectric1 but after Dishing and Erosion, it become part of Dielectric2.
  • Now when you will deposit Metal2 on such surface, starting level of Metal2 automatically shifted (because it has dependency on the Top level of Dielectric1 (which is effected by Erosion).
  • After CMP on Metal2 and Dielectric2 structure leveling again distorted and dishing and Erosion will again take place.
  • Region4, which is originally assigned to Dielectric2 now will be part of Dielectric3.
In short I can say that:
  • Non-uniform copper and dielectric loss on M1 compounds the losses on M2 and higher metal levels.
  • CMP effects are cumulative
  • Multilevel effects impacts DOF (depth of focus), etch, and ultimately yield.

Note: These irregularity in the above figure is zoomed for your understanding but actually it’s far far better than the irregularity introduced when you will not do the CMP.  The reason I made this statement so that you don’t ask me that before and after there are irregularities, so why do CMP?  I have also explained this later.

Note: There are few recommended solution which can mitigate the effect of CMP like dummy filling and pillars/holes put in large width interconnects. I will discuss those later (this statement is going to support above Note and if same question came into your mind).

Same thing I have tried to cover into the 3D view. It may not be as accurate but you can understand what I am trying to convey.
  • Ideally:
    • Same metal thickness with certain level of leveling (from starting and ending point of view)
    • Constant Dielectric thickness and leveling across the wafer.
  • But after CMP:
    • Thickness of Metal layer changes
    • Dielectric leveling changes (Dielectric thickness Changes).
    • CMP effect Cumulates and affects other metal and Dielectric layers.

To justify my comment which I have made above that irregularity introduced by CMP is not same as before CMP, I have drawn few figure (tried my best) … (ufff few more figures).
After seeing the below figures, I am sure you can easily understand the differences and the importance of CMP. Best part is there are ways to minimize the side effect of CMP (Erosion and Dishing issue) with the help of few best practices + few other methods.

For higher nodes (like 90nm and above) these manufacturing issues are captured using the certain values based on width, spacing, density, thickness directly (also known as rule based approach via lookup tables or in the form of polynomial equations). These are present in the technology file used by extraction tool. Just an fyi that technology files are process dependent and created based on the information provided by the foundries like ICT and ITF file (We will discuss about these files later).

For lower nodes (below 90nm), due to the complexity of the process (multi-level effect) and dependency on lot of parameters (pressure, temperature, speed, pad material, slurry material etc.) it’s very difficult to exact model these variation using rule based approach.
Complexity of CMP process can be easily understandable by the following slide (captured from Internet).

Foundry and other partners develop a simulation based approach in which they take account of different effects, physical (Pad property, pressure, polish time, etc.) as well as chemical effects (slurry type, remover rate, etc.), and simulates the physical CMP process. In this approach as per the process and the design different hotspots are usually identify and accordingly corrective methods are applied. This approach is more accurate in comparison to rule based because
  • It’s not generic. It’s design dependent.
  • Different process parameters are considered and their effects are evaluated on the design. If any particular parameter can be neglected (on the basis of result), we can ignore that part also.
  • In rule based, to cover all sort of design a lot of pessimism has to be added, which can be ignored here (because it’s design dependent). It reduce pessimistic design guard band through more accurate timing/power analysis.
  • CMP model based approach also helps dummy fill optimization as compared to current rule (density) based approach (same reason as in above point – In the rule based, we have to add extra pessimism)
Note: RC Extraction can also use these “Data” for more accurate calculation of R and C. There are few Tools available in the market (like CCP – Cadence CMP Predictor, Prime-Yield).

In the next part, we will discuss about the Erosion and Dishing in detail.

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