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Sunday, July 19, 2015

CMP (Chemical Mechanical Planarization) (Part 1: Introduction)



Introduction to CMP (Chemical Mechanical Planarization)


Index Chapter1 Chapter2 Chapter3 Chapter4
Introduction Parasitic Interconnect Corner (RC COrner) Manufacturing Effects and Their Modeling Process Variation


3.1 3.2a 3.2b 3.3a 3.3b 3.3c
Introduction Effect Of Etching Process Effect Of Etching Process Introduction to CMP (Chemical Mechanical Planarization) Importance Of CMP process Dishing and Erosion (CMP effects)

Let’s first try to remind you the summary of very first article of this series. Below diagram can help you.


We are trying to study different manufacturing Effects which directly or indirectly effects Parasitic (RC) Extraction. CMP (Chemical Mechanical Planarization) is one of the important step from fabrication point of view and it play an important role in adding defects in the manufactured chip.

It’s a process of smoothing and planning the surfaces with the combination of chemical and mechanical forces. This process is a hybrid process of Chemical etching and free abrasive polishing. Individually,
  • Chemical etching cannot do planarization because of chemical reaction is isotropic in nature (For reference, you can refer ETCHING articles).
  • Similarly, Mechanical grinding for planarization alone is not sufficient (Theoretically it looks like it’s possible but practically a lot of challenges come). The chances of Surface damage is high in case of only mechanical grinding.
CMP has many advantages over standard “Reactive Ion Etching” (RIE) processes.
  • RIE processes cannot readily etch copper. CMP does a very good job removing copper.
  • In case of RIE process it’s difficult to etch the SiO2 and other dielectric layer smoothly. While CMP is mainly used for silicon dioxide, polysilicon, copper,low-κ dielectrics, and tungsten removal and planarization for the semiconductor wafer surface while at the same time producing a surface that is both very smooth and flat.
In CMP, as I have mentioned that it’s a hybrid process, it’s first calculate the degree of irregularities in the wafer and then make sure that high points on the wafer would be subjected to higher pressures from the pad as compared to lower points, hence, enhancing the removal rates there and achieving planarization.
You may not understand properly but may be below figure can help you in that.


In the above figure, assume that “a” is the intermediate stage of wafer (after few fabrication step) and now we have to add/deposit the “Copper Metal” for creating the Metal wires. Ideally, you are expecting something similar to “b” (Even I have explained the same in one of my previous article in the similar fashion). But point to be noted – I have used the word “Ideally”.  . Practically, it’s different – It will be something similar to “c”. Not plane surface at the top. You can’t use the same for next step because of these irregularities in the Metal layer. That’s why planarization is required and as I have explained above, CMP is the process of doing this. 

CMP is an elegant process and can be completed in a semiclean environment in the wafer fab. For understanding the process (how it perform actually in the Fabrication lab), you can watch below video.
EMBEDDED Video



Just try to explain also with the help of above diagram. Where you can see how polishing pad is used for planarization of wafer. Polishing table and Wafer Carrier usually rotate in different direction (at least at different axis), so rubbing action is sure. Rest details, I am sure you can figure out through the video.

For more understanding the importance of this, again refer the below figure.


Figure “a” is the wafer condition just before the Metal layer Deposition. Ideally after deposition, you need something similar to fig “b” but practically it’s difficult to fill only the “white spaces”, so in general you drop the metal completely which will automatically fill the “White Spaces” along with spreading in rest of the area also. Like in figure “c”. That’s the reason we need CMP process to remove the unwanted Metal (which also spread over the wafer) and creating shorts across all metal layers. As I am saying creating a shorts – so you can understand how important to do this precisely (means to ensure complete copper removal across the entire wafer).

More clear view in 3D


Remember with the help of CMP – we want to move from “c” to “b” or say achieve “b” structure from “c”.
Now it’s time to ask few questions from you –
  • Is it possible to get exact as we need after CMP process or not?
  • Is there any Disadvantage or say side effect of this process.
  • If yes, what are those? And how they impact the overall functionality.
Answer of all the questions are based on thing. There is nothing in this world without any side effect.  
CMP process has several potential defects (Side Effect) including
  • Stress cracking,
  • Delaminating at weak interfaces, and
  • Corrosive attacks from slurry chemicals.
These are due to the several process factors which play an important role in the CMP like Pressure, velocity, slurry composition.
During the CMP process, friction easily changes the temperature (near about 10degree increase compare to surrounding temperature). As the temperature rises, removal rate also increases (because of several reason – like chemical reaction act differently in high temp, softness also changes with high temperature).

Copper Dishing and SiO2 Erosion are 2 main surface defect which are result during the over-polishing step (which is required to ensure complete copper removal across the entire wafer) of CMP process. We will discuss these things in detail in next Article.

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