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Friday, October 9, 2015

Metal Width Variation (Type 4 and Type 5)

Metal Width Variation (Part 3)

Width Variation Type 4:


Variation type 3 has condition that
  • Top width delta on either side should be same
  • Bottom width delta on either side should be same.

I know you can say that it’s easy and let’s divide the modeling parameter top and bottom into left and right side. Like bottom_left, bottom_right, top_right and top_left. But it’s not as easy as you are thinking. Because these modeling has some background. We have to think, what are different reasons which can output different left and right delta? Even I am trying to figure out the exact reason of that (if you find, please let me know ). Point is, I will update you later but till then you have to search out. 

Just a hint that width variation also depends on the surrounding environment (like metal density or say space with respect to neighboring metal layer). So in this variation type, we have to consider the fact that width variation also depends on the space with respect to neighboring metal wire. In such case foundry provide below type of info.

Table 7: Metal effective Silicon Width based on Drawn Width and Spacing pattern
Metal Drawn Width (um) Drawn Space (um) Silicon Width (um)
Metal 1 0.5 0.5 0.409
Metal 1 0.5 0.75 0.429
Metal 1 0.5 1.0 0.439
Metal 1 0.5 1.5 0.448
Metal 1 0.75 0.5 0.682
Metal 1 0.75 0.75 0.701
Metal 1 1.0 0.5 0.930
Metal 1 1.0 1.0 0.960
Metal 1 1.0 1.5 0.969
Metal 1 1.5 0.5 1.420
Metal 1 1.5 1.0 1.449
Metal 1 1.5 1.5 1.459

Similar type of table you can get for other metal layers with more spacing and width points. These are just for the reference level. Also remember – in place of Silicon Width, info can be in the form of delta value or delta %. It depends on foundry to foundry. 

Sometime same info can be provided into following way (final silicon width with respect to different drawn width and spacing combination)

Table 8: Metal effective Silicon Width based on Drawn Width and Spacing pattern
w/s 0.1000 0.1300 0.1500 0.2000 ...
0.1000 0.1025 0.1125 0.1220 0.1470 ...
0.1300 0.1265 0.1285 0.13400.1525 ...
0.1500 0.1459 0.1459 0.14590.1599 ...
0.2000 0.1783 0.1783 0.17830.1783 ...
... ... ... ... ... ...

You may ask now, how it will remove the constraint of Type 3 variation. Very simple… left and right side variation in width can be figure out as per the environment around a particular metal layer. Please refer below figure for more understanding. It will help you to understand how left and right variation can be coded differently without using “left” and “right” keywords.


With the help of combination of different type of variation we can model anything. Like different top and bottom delta (using Type variation 3), different left and right delta (using type variation 4). As I have described in type3 how to combine different variation types, same process we can use along with Type 4 and come more closure to actual silicon structure.


Note: In above figure X1, X2, X3 and X4 can be equal or may be different.
Using the variation type 4 (along with other variation type), we are more closure toward the actual shapes after the manufacturing. Please refer the below comparison. (Note: here bottom_delta and top_delta are different along with right and left bottom variation also).



Width Variation Type 5:


Question is what’s now missing. There is one point which we are assuming continuously that variation will be linear in shape from top to bottom but in actual that’s not the case. Like in the below figure.


What’s the solution of that! Very simple – provide the equation or “order of polynomial equation” of variation from top to bottom. 
Fortunately, till now I didn’t come up with any such data provided by Foundry. May be it’s not that important till now or Foundry don’t want to make modeling so complex.(Good for EDA vendor). But this is a proposed solution from me for future. 

Reference: "Including Pattern-Dependent Effects in Electromagnetic Simulations of On-Chip Passive Components" by Sharad Kapur, David Long, Tsun-Lai Hsu, Sean Chen, Chewn-Pu Jou, Sally Liu, Gwan-Sin Chang, Cheng-Hung Yeh, and Hui-Ting Yang (Download)

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