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Monday, February 28, 2011

Basic of Timing Analysis in Physical Design

Lots of people asked me to write over timing analysis. Though a lot of material is present but still most of the people are not 100% sure about all these concepts. I am trying to put few of the things here in a simpler language and hope that it will help (beginner and professional).
Please let me know if anybody thinks that I should add few more things here. It’s difficult to put everything in one blog so just consider this as the first part of Timing analysis.

What is Timing Analysis??

Before we start anything at least we should know what exactly we mean by Timing Analysis. Why these days it’s so important?

There are a couple of reasons for performing timing analysis.
  • We want to verify whether our circuit meet all of its timing requirements (Timing Constraints)
    • There are 3 types of design constraints- timing, power, area. During designing there is a trade-offs between speed, area, power, and runtime according to the constraints set by the designer. However, a chip must meet the timing constraints in order to operate at the intended clock rate, so timing is the most important design constraint.
  • We want to make sure that circuit is properly designed and can work properly for all combinations of components over the entire specified operating environment. "Every Time".
  • Timing analysis can also help with component selection.
    • An example is when you are trying to determine what memory device speed, you should use with a microprocessor. Using a memory device that is too slow may not work in the circuit (or would degrade performance by introducing wait states), and using one that is too fast will likely cost more than it needs to.

So I can say Timing analysis is the methodical analysis of a digital circuit to determine if the timing constraints imposed by components or interfaces are met. Typically, this means that you are trying to prove that all set-up, hold, and pulse-width times are being met.

Note: Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be compromised but not timing!

Types of Timing Analysis:

There are 2 type of Timing Analysis
  • Static Timing Analysis
    • Checks static delay requirements of the circuit without any input or output vectors.
  • Dynamic Timing Analysis.
    • verifies functionality of the design by applying input vectors and checking for correct output vectors
Basic Of Timing Analysis:

The basis of all timing analysis is the clock and the sequential component (here we will discuss with the help of Flip-flop) . Following are few of the things related to clock and flip-flop which we usually wants to take care during Timing analysis.

Clock related:
  • It must be well understood parametrically and glitch-free.
  • Timing analysis must ensure that any clocks that are generated by the logic are clean, are of bounded period and duty cycle, and of a known phase relationship to other clock signals of interest.
  • The clock must, for both high and low phases, meet the minimum pulse width requirements.
  • Certain circuits, such as PLLs, may have other requirements such as maximum jitter. As the clock speeds increase, jitter becomes an increasingly important parameter.
  • When "passing" data from one clock edge to the other, ensure that the worst-case duty cycle is used for the calculation. A frequent source of error is the analyst assuming that every clock will have a 50% duty cycle.
Flip-Flop related:
  • All of the flip-flops parameters are always met. The only exception to this is when synchronizers are used to synchronize asynchronous signals
  • For asynchronous presets and clears, there are two basic parameters that must be met.
  • All setup and hold times are met for the earliest/latest arrival times for the clock.
  • Setup times are generally calculated by designers and suitable margins can be demonstrated under test. Hold times, however, are frequently not calculated by designers.
  • When passing data from one clock domain to another, ensure that there is either known phase relationships which will guarantee meeting setup and hold times or that the circuits are properly synchronized
Now Lets talk about Each type of Timing analysis One by one in the next few blogs.



  1. Excellent pieces. Keep posting such kind of information on your blog. I really impressed by your blog.

  2. really good site to clear our doubts

  3. Really great job!!! very helpful

  4. I don't know how to address you. Until I know you, will stick to Senior.

    Senior, what we loosing by limiting our selfs to static analysis to fix all the timing issues?

    In real world every thing is dynamic. We do functionality verification with vectors, we simulate ( or emulate if we could afford it. ), which is dynamic !

    But coming to timing we are limiting to static analysis because of resources ( machine time and to reduce the run time of incremental timing analysis by the 'Design automation tools' during synthesis, place n route stages).

    This is costing us something for sure... Am trying to figure it out !


  5. My Mentor told me when ever you come to me with a question, "I also want you bring along all the possible answers, on the basis of your experience and knowledge".

    Senior, in the early days when our fathers decided to stick to timing analysis for only 'Static', we are only needed few more days of work to tune the constraints to reflect dynamic situations of the design application.
    i.e timing exceptions.
    If the timing analysis is dynamic, we don't need to add timing exceptions, in the real dynamic time they don't happen.

    In the current world of system on a single chip, there are too many variable ( a wide variety of IPs ) for engineers to figure out all the timing exceptions that won't occur in the real time.

    I personally witnessed and suffered how not clean constraints munching valuable turn around time for todays complicated SOC design's specs to silicon realization.

    Conclusion : By not doing dynamic timing analysis, we are loosing valuable time and all stages of chip design are suffering. Considering my limited experience and knowledge this might be a false conclusion, please comment.

    The possibility ( or impossiblity ) of implementing a dynamic timing analysis is completely different discussion, and I need to reach out my peers in EDA software development industry to comment on this.


  6. thanks bro for the blog i am searching for this for a long time thank u so much

  7. very informative ...thanks a lot


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