## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Sunday, December 31, 2017

### Timing_sense : Timing Arc in .LIB Files (Part2)

 STA & SI:: Chapter 1: Introduction 1.1a 1.1b 1.1c 1.2a 1.2b INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

### Representation of The Unateness of timing Arc In timing Library:

In last article, we have discussed about the representation of Timing arc with respect to Logic gates in .lib file. In the Timing Library, "Timing Arc information" is stored with the syntax "timing_sense".

In this article, we are trying to extend timing arc concepts from simple "Logic gate" to complex combinational circuit. We will start with few standard logic functions like AOI (AND-OR-Inverter), OAI (OR-AND-Inverter). Then we will discuss about the few standard combinational circuits like MUX.

1) For Multiple Input and Single Output

AOI Gate: 3 Input and 1 Output: Y=((A.B)+C)'

To understand the circuit diagram and operation of AOI please refer Article AND-OR-Inverter

/* --------------- *
* Design : AOI21X1 *
* --------------- */
cell (AOI21X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.0179;
rise_capacitance : 0.0170;
fall_capacitance : 0.0173;
}

pin(B) {
direction : input;
capacitance : 0.0179;
rise_capacitance : 0.0174;
fall_capacitance : 0.0179;
}

pin(C) {
direction : input;
capacitance : 0.015;
rise_capacitance : 0.015;
fall_capacitance : 0.015;
}

pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.5;
function : "(!((A B)+C))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
.....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
.....
}
timing(C_Y) {
related_pin : "C";
timing_sense : negative_unate;
.....
}
....
}
.....
}

AOI Gate: 4 Input and 1 Output: Y=((A.B)+(C.D))'

/* -------------- *
* Design : AOI22X1 *
* -------------- */
cell (AOI22X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(C) {
direction : input;
....;
}
pin(D) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(!((A B)+(C D)))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
}
timing(C_Y) {
related_pin : "C";
timing_sense : negative_unate;
....
}
timing(D_Y) {
related_pin : "D";
timing_sense : negative_unate;
....
}
....
}
}

OAI Gate (OR-AND-Inverter): 4 Input and 1 Output: Y=((A+B)(C+D))'

/* -------------- *
* Design : OAI22X1 *
* -------------- */
cell (OAI22X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(C) {
direction : input;
....;
}
pin(D) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(!((A+B) (C+D)))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
}
timing(C_Y) {
related_pin : "C";
timing_sense : negative_unate;
....
}
timing(D_Y) {
related_pin : "D";
timing_sense : negative_unate;
....
}
....
}
}

Multiplexer: 2x1 MUX.

Multiplexer (2x1 MUX) has 2 Input pin, 1 Select pin and 1 output pin. Select pin is also a Input pin (whenever you see .lib file its very clearly defined as input pin). Now, we need to understand the relationship between different input and output pin. To understand this relationship, either you have internal circuit diagram or you can draw truth table or you can use the equation method. Let's see here with respect to equation.

MUX Input output equation is:
Y = (S'.A) + (S.B)

If you remember, previously we have discussed how you can figure out the unateness of output with respect to individual Input from equation (or say function) directly. Just in case, you want to revise, please check Unateness using Function Method.

From equation, it's clear that:
• Y is Positive Unate with respect to input pin A.
• Y is Positive Unate with respect to input pin B.
• Y is Non-unate with respect to Select line S.

Note: You can try other method your own. For more detail of these methods, please refer Article "Unateness in Complex Circuit".

Now, let's see .Lib representation of this.

/* -------------- *
* Design : MUX2X1 *
* -------------- */
cell (MUX2X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(S) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "((!S A) + (S B))";
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : positive_unate;
....
}
timing(S_Y) {
related_pin : "S";
timing_sense : non_unate;
....
}
....
}
}

Multiplexer: 2x1 MUX (Other configuration)

When I was checking the MUX with in the .Lib file, I come across another configuration. It's difficult to explain that here but with the help of equation you can easily figure out.

Y = ((S.A) + (S'.B))'

From this equation, you can easily say that
• Y is Negative Unate with respect to input pin A.
• Y is Negative Unate with respect to input pin B.
• Y is Non-unate with respect to Select line S.

Now, .lib representation is also very clear. :) Only Output Y section

pin(Y) {
direction : output;
....;
function : "(!((S A) + (!S B)))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
}
timing(S_Y) {
related_pin : "S";
timing_sense : non_unate;
....
}
....
}

2) For Multiple Input and Multiple Output

You might be thinking about any logic gates having multiple output. I would say forget about that and try to understand how to represent such circuit in .LIB file. Below are 2 output function which I can see in my .lib file (Snapshot of .LIB which I have) for a particular CELL.

YC = ((A B)+(B C))+(C A) &
YS = (A^B)^C

Note: I am sure after seeing Equation, you must have figured out the circuit I am talking about. :) Yes, It's a Fully Adder Circuit. Similarly, you can have Half Added Circuit as part of your Library. :)

/* -------------- *
* Design : FAX1 *
* -------------- */
cell (FAX1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(C) {
direction : input;
....;
}
pin(YC) {
direction : output;
....;
function : "(((A B)+(B C))+(C A))";
timing(A_YC) {
related_pin : "A";
timing_sense : positive_unate;
....
}
timing(B_YC) {
related_pin : "B";
timing_sense : positive_unate;
....
}
timing(C_YC) {
related_pin : "C";
timing_sense : positive_unate;
....
}
....
}

pin(YS) {
direction : output;
....;
function : "((A^B)^C)";
timing(A_YC) {
related_pin : "A";
timing_sense : non_unate;
....
}
timing(B_YC) {
related_pin : "B";
timing_sense : non_unate;
....
}
timing(C_YC) {
related_pin : "C";
timing_sense : non_unate;
....
}
....
}
}

I am sure, by now you are very much clear about the representation of Unateness in .LIB file for all logic gates and few Standard combinational circuit. Any circuit which is similar to this, you can easily understand the input-output relationship just by seeing these few (direction, related_pin, function, timing_sense) parameters in the .Lib file. Or you can write any .lib file if you already have input-output relationship.

Now, there are few special Cells like TriState Cell (e.g TriState Buffer) and Sequential Cells like D flipflop which are still untouched in our discussion. For that we have to introduce few new parameters as a part of Timing Arc. Let's discuss those in next articles.

Happy Learning