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Tuesday, September 9, 2014

Creating Gate Oxide and Poly Layer: CMOS Processing (Part3)

Creating Gate Oxide and Poly Layer

Index Chapter1 Chapter2 Chapter3 Chapter4
Semiconductor Background CMOS

3.1 3.2 3.3 3.4 3.5 3.6
N-Well and Field Oxide
Gate Oxide and Poly Layer
N+ Impurities
P+ Impurities
Metal Contact

Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different Articles as per above table.

Let’s start with the 3D diagram of silicon wafer where we left in the last post.

In the last post we have talked about the Field Oxide and here is Gate oxide. The gate oxide is the dielectric layer (silicon Oxide) similar to the Field Oxide but very thin in size. It separates the gate terminal of a MOSFET from the underlying source and drain terminals.
Final 3D diagram of silicon wafer.

Now we will deposit the polysilicon layer which will act as GATE contact. This Polysilicon layer also known as POLY in short.

Poly layer above the gate oxide is also known as GATE POLY and the poly above the Field Oxide also known as FIELD POLY. In other word, you can say that POLY with in the active region is known as GATE POLY because it helps in forming the Gate of Device and POLY outside the active region is known as FIELD POLY.

Final 3D Diagram of Silicon Wafer :

Till now we have created
  • Nwell
  • Active Region
  • Channel Stop Region
  • Field Oxide.
  • Gate Oxide
  • Poly layer.
In the next post we will talk about adding N+ impurities which will help us to create NMOS devices.

Saturday, September 6, 2014

Create N-well And Field Oxide: CMOS Processing (Part 2)

Create N-well And Field Oxide

Index Chapter1 Chapter2 Chapter3 Chapter4
Semiconductor Background CMOS

3.1 3.2 3.3 3.4 3.5 3.6
N-Well and Field Oxide
Gate Oxide and Poly Layer
N+ Impurities
P+ Impurities
Metal Contact

If you think, I can explain the complete manufacturing steps in a single post then it’s not possible. So I will discuss this in a series of 4-5 post. Best part is – I will try to explain more with pictures and explain them in very short (in text). I will only discuss the concepts in between (if required). I have tried to make figures/diagram self explanatory. But still in case of confusion, feel free to ask me.
Complete CMOS fabrication, I have divided into different post based on below milestones.
We want to fabricate a CMOS Inverter.


In the above diagram – you may have few questions and doubts. Let me add few points here which can help you.
  • Only Photoresist is not sufficient to shield Silicon from Ion Implantation. So Oxide or Nitride is required to block the implant.
  • There are 2 portion of Photoresist. Soluble/Soft portion (Portion on which UV rays falls) and Hard portion (Which is not exposed by UV)
  • Solvent required to remove/dissolve the soft portion of photoresist is different from the solvent required to remove the hard portion.
  • For CMOS process, both NMOS (N- Channel transistor) and PMOS (P-Channel transistor) are required. 
    • For NMOS – P-type substrate is required
    • For PMOS – N-type substrate is required.
We always talk about the P-type substrate and Not N-type Substrate. Question is why?
It’s not like P-Type substrate is available in the market and we are just using that. In the Market Silicon wafer is available and with the help of Doping – we convert that silicon wafer into P-type substrate. Now you will ask why we can’t convert this into N-type Substrate. And I will simple say – you can do that. No one is going to stop you. They why it’s not well known?
Actually – we can’t use 2 different substrate for design because in the design both PMOS and NMOS is present. We have to choose which is more beneficial from fabrication point of view. In general or say it’s true that NMOS devices are always more in the Semiconductor Industry in comparison to PMOS devices. For your reference-SRAM requires 6 transistors (4 NMOS, 2 PMOS)

Another reason for more number of NMOS is because of difference of mobility of electron and Holes. Electron mobility is almost twice of holes mobility and because of this ON-RESISTANCE of n-channel device is half of p-channel device with the same geometry and under the same operating conditions. That means to achieve same impedance size of n-channel transistors is almost half of p-channel devices. Same thing I can say in the different way that for same size of wafer, we can have more number of NMOS (means can perform more logical operation) in comparison to PMOS.

I hope above explanation helps you to understand the reason of well-known P-type Substrate. :) 
  • For NMOS – we doped entire silicon wafer first with P-type impurities and make it P-type Substrate, where we can directly form N-channel devices.
  • For PMOS – we have to separately create N Well selectively (by adding N-type Impurities in the selective regions).

Twin Tub (Twin-Well) CMOS Process:

There is a process where both type of Wells (N- Well and P Well) are present. Such process is known as Twin Tub (Twin-Well) CMOS process.

This process is required when we want to optimize different parameters independently (like threshold voltage, body effect and the channel transconductance). If we have p-type of substrate then all the NMOS can’t be optimized independently (because they have common P-type substrate). Similarly N-well is with in P-substrate, then there is some influence of this on PMOS also. I am not going to discuss all this right now. It’s just for your info. 

Device Isolation/Field Oxide (Channel Stop implants)

As I have mentioned above for better performance Devices should be electrically isolated from each other (both same type and different type of devices). Basically we want to suppress leakage current.

Best solution is to form a reverse bias pn-junction between 2 transistors. That means if we form positive doped region next to the negatively doped region (N-well next to P-well or vice versa), they can automatically form a reverse bias between 2 regions. Till the point there is a depletion layer between them, except reverse saturation current (very small leakage current) there will be no electrical connection between these 2 regions until voltage exceed breakdown voltage. To control the voltage between these 2 regions, we can tie n-region to most positive voltage (VDD) and p-region to most negative voltage (VSS).

Junction leakage current has dependency on the area of the depletion layer, so in case of large n and p region, this current will be significant and it will not solve the complete purpose.

In such cases, there is another general method – forming the dielectric layer between 2 transistors. This dielectric is very thick and known as Field Region (Field Oxide).
Few points about the Field Oxide
  • Also known as Thick Oxide, Thick SiO2 insulator.
  • Field Oxide is Thickest Oxide relative to other oxide layer present in the IC (e.g. Gate Oxide layer)
  • This oxide region is different from the Gate oxide.
  • The area where Field Dielectric is not present, is the area where Transistor exist. And this area is known as active region.
  • There are 2 ways to form the Field Oxide Region (We will not discuss these 2 methods right now).
    • LOCOS (LOCal Oxidation of Silicon).
    • STI (Shallow Trench Isolation)
Field Oxide increases the transistor’s threshold voltage so that device always remains in Off-stage. This threshold voltage can be further increased by increasing the surface doping concentration, Called “Channel Stop” under the Field Oxide.

So the Isolation region are formed by 2 layers
  • Channel Stop Implants/region (p+)
  • Field Oxide layer
To increase the threshold voltage as much as possible, Channel shop region should be highly doped and Field Oxide layer should be as thick as possible.

Size of above final figure is small for clarifying the further processing. So now I am just expanding that and start the process from there on.

End results will be something similar to the below one (in 3D).

Till now we have created
  • Nwell
  • Active Region
  • Channel Stop Region
  • Field Oxide.
In the next post we will talk about Gate Oxide.


Thursday, September 4, 2014

Fabrication Steps: CMOS Processing (Part 1)

Fabrication Steps: CMOS Processing

Index Chapter1 Chapter2 Chapter3 Chapter4
Semiconductor Background CMOS

3.1 3.2 3.3 3.4 3.5 3.6
N-Well and Field Oxide
Gate Oxide and Poly Layer
N+ Impurities
P+ Impurities
Metal Contact

Property of material plays a very important role on the performance of MOSFET devices. If you are not agreeing with this statement, then maybe you have to refer device physic. But now just believe me. J
While we are fabricating the MOSFET, we have to take care about the different material used based on the performance of end product (MOSFET) and so we can say that properties of the material (which material, doping, sizes …) come from the Fabrication of the MOSFET. In this post, I am going to brief you about the different Fabrication steps of CMOS device and some important info which will help you to understand different terminology + fundamental of lower technology node process.
Just few basics:
Materials can be classified in to 3 main groups as per their electrical conducting property.
  1. Insulator
    • Used to isolate conducting or semiconducting material from each other.
    • MOS devices and Capacitance require insulator for their physical operation.
    • Which insulator is required – it depends on the functionality for which you want to use it.
    • Few of the known insulators are
      • Silicon Dioxide
      • Silicon Nitride
  2. Conductor
    • Conductors are used in the IC world for electrical connectivity.
    • These are used as Local interconnects, Global Interconnects and in Contact/VIAs.
    • Few of the good conductors are:
      • Silver
      • Gold
      • Copper
      • Aluminum
      • Platinum
  3. Semiconductor
    • This is the base of whole semiconductor Subject. Silicon is the known semiconductor material.
    • This is very popular because of
      • Physical characteristic
      • Low cost because of easily available in the nature.
      • Selective doping of various regions of silicon allows the conductivity of the silicon to be changed with the application of voltage.
    • Other semiconductor material is GaAs but this use only for specific purpose/applications.
There are lot of processing technology are available in the market but only few are very popular. Out of which majority of production is done with Traditional CMOS. Others are limited to the area where CMOS is not very suitable (like High speed RF applications).

Few important concepts about the fabrication

  • ICs are created on Silicon Wafer.
  • Silicon Wafer is a very think disk of intrinsic Silicon on which rectangular or square shape of multiple ICs are created.
  • Individual ICs are cut with the help of diamond saw and marked as pass or fail after proper testing.
  • The individual IC is called a “die”

  • On the basis of good no of die in a wafer, we define a term YIELD.
Yield = (No of Good die)/(Total No of die on the wafer)
  • We always try to achieve 100% yield but that’s the ideal scenario. In a mature technology node or say process Yield approximately equal to 90%.
  • Always remember – Yield decides the cost of the chip.
  • All ICs on a same wafer are processed at the same time, so the time taken and process steps are same regardless the no of ICs in silicon wafer.
    • This means the cost to process a wafer is the same whether it has 1 IC, or 1000 IC’s on it or not.
    • Lower technology node process (e.g. 45nm) has more number of die in silicon wafer in comparison to higher technology node process (e.g. 180nm). 
Now we will understand few of the terminology which is linked with the Fabrication and now-a-days are more know to outside world. I will not discuss too much about these because we need not to know the every details (like equations, equipment in each process and all) of these steps. I will try to cover as much as possible which is required/ sufficient for CMOS fabrication point of view.



Note: In case you are interested in more details about this process, you can refer chapter 3 of VLSI Technology by S.M SZE.

Oxidation of Silicon is necessary throughout the IC fabrication process. SiO2 plays an important role in IC technology because no other semiconductor material has a native oxide which is able to achieve all the properties of SiO2. Silicon Dioxide has several uses:
  • To serve as a mask against implant or diffusion of dopant into the silicon
  • To provide the surface passivation (creating protective SiO2 layer on the wafer surface). It protects the junction from moisture and other atmospheric contaminants.
  • To isolate one dielectric from other.
  • SiO2 acts as the active gate electrode in MOS device structure.
  • Used to isolate one device from other.
  • To provide the electrical isolation of multilevel metallization system.
Several techniques are there for forming oxide layer and each technique has their preferred uses.
  1. Thermal Oxidation
    1. When the interface between the oxide and the silicon requires a low charge density level, thermal oxidation has been preferred technique.
  2. Vapor-Phase technique
    1. Also know as Chemical Vapor Deposition (CVD)
    2. When oxide layer is required on the top of a metal as in case of multilevel metallization structure, vapor-phase technique is preferred technique.
Just as a general principal and which you will see later – When Silicon exposed to oxygen – silicon dioxide form rapidly.  Remember – Silicon got consumed during this process.
There are 2 ways of doing oxidation. I can help you with the equations.

Si (Solid) + O2 -> SiO­2 (Solid)

  • This process is known as Dry Oxidation.
  • No byproduct.
  • Form a thin layer of Silicon Dioxide.
Si (Solid) + 2HO2 -> SiO­2 (Solid) + 2H2
  • Know as Wet Oxidation.
  • Hydrogen (H2) is the byproduct.
  • Forms a thick layer of Silicon Dioxide.
  • If heat is added to the process, the rate of SiO2 growth is sped up considerably
  • This is called “Thermal Oxidation” which applies to both Wet and Dry processes
  • Temperatures usually are in the range of 700 – 1300 C
Oxidation of Silicon surface:
Oxidation through a window in the oxides:
Selective Oxide Growth:

Note: above 3 diagrams are captured from CMOS Processing link.


Note: In case you are interested in more details about this process, you can refer chapter 4 of VLSI Technology by S.M SZE.
A technique used in IC fabrication to transfer a desired pattern onto the surface of a silicon wafer. The word lithography comes from the Greek lithos, meaning stones, and graphia, meaning to write. It means quite literally writing on stones. In the case of semiconductor lithography (also called photolithography) our stones are silicon wafers and our patterns are written with a light sensitive polymer called a photoresist.
Few important points to know about photolithography:
  • Process of lithography can be accomplished by selectively exposing parts of the wafer while other parts are protected.
  • The exposed sections are susceptible to doping, removal, or metallization.
  • Specific patterns can be created to form regions of conductors, insulators, or doping.
  • Due to the large number of lithography steps needed in IC manufacturing, lithography typically accounts for about 30 percent of the cost of manufacturing.
  • Designer do the following things:
    • Drawing the “layer” patterns on a layout editor
  • Silicon Foundry:
    • Generate the Mask as per the layer pattern provided by Designer.
    • Transfer the mask pattern to the wafer surface.
    • Process the wafer to physical pattern each layer of the IC.
Lithography Process:
  • Photoresist coating:
    • A material that is acid-resistant under normal conditions.
    • When exposed to UV light, the material becomes soluble to acids
    • We put the photo resist on a wafer.
    • There are 2 type of photo resist. Positive and Negative. Positive Photoresist is the most popular due to its ability to achieve higher resolution features
Original State
After UV Exposure
“Positive Photoresist”
“Negative Photoresist”

  • Exposure:
    • Mask pattern is developed as per the design.
      • A mask in an opaque plate (i.e., not transparent) with holes/shapes that allow UV light to pass
      • The mask contains the pattern that we wish to form on the target wafer
    • We pass the UV light and expose the photoresist region selectively as per the pattern present in the Mask.
    • UV rays create a soluble pattern in the photoresist. Depending on the type of photoresist (negative or positive), the exposed or unexposed parts become resistant to certain types of solvents.
    • Apart of UV light there are other type of exposing radiation are also present.
      • Electron, X-rays or ions

  • Development:
    • Then we can soak the entire thing in acid/solvent and only the soluble photoresist (depends on positive or negative photoresist) is removed.
    • The developed photoresist acts as a mask for patterning of underlying layers. We can also say that this allows us to form a protective barrier on certain parts of the wafer while exposing others parts.


Just few points about etching. More in details you can refer my other post.

  • Once the desired shape is patterned with photoresist, the etching process allows unprotected materials to be removed.
  • Etches can remove Si, SiO2, polysilicon, and metal depending on what we want to accomplish.
I was just reading an article and like below definition of this step. I hope you will also like it.
The Process which immediately follows the photolithography step is the removal of material from areas of the wafer unprotected by photoresist.

When I am going to discuss the different steps of CMOS fabrication in next few posts, you will get a very clear picture


Deposition is the process of laying down a thin film of material on the surface of a silicon wafer. During chip designing we use several such films. It is opposed of growing where it consumes part of the target / wafer (like Oxide Growth)



Note: Copied the above diagram from Internet.


Few important things about the deposition:

  • These layers form wires and insulators that interconnect all the transistors of the device.
  • Material examples are:
    • SiO2, nitride, poly, metal
    • Materials are divided into 4 categories.
      • Metal
        • Aluminum alloys
        • Tungsten
        • Titanium Nitride
      • Silicides
        • Tungsten
        • Molybdenum
        • Titanium
      • Polysilicon
      • Dielectric
        • Silicon Dioxide
        • Silicon Nitride
        • Phospho-silicate Glass
        • Boro-phospho-silicate Glass
As per the process of Deposition it’s classified into 3 major areas
  1. Chemical Vapor Deposition (CVD)
    • This method are commonly used for depositing
      • Polysilicon
      • Dielectric
      • Metals
      • Silicides
    • The films created by this method are uniform films with excellent step coverage.
    • This method is very economical. Just chemical reaction is the limitation.
  2. Physical Vapor Deposition (PVD)
    • It involves the physical removal of material from a target via ion bombardment. This is similar to sand blasting.
    • Film material flies away from the target and adheres to the wafer, making the desired film.
    • It can be used to deposit any material on any substrate. Because it’s a physical in nature and doesn’t rely on a chemical reaction.
    • This method is not as economical as CVD
    • This method are commonly used for depositing
      • Aluminum
      • Gold and their alloys.
  3. Epitaxy
    • It’s a unique form of CVD. The purpose of epitaxial deposition is to grow additional single crystal silicon above the original wafer surface.
    • It’s a very expensive method and only used in the MOS processing.
    • Silicon
    • MBE
    • MOCVD

Ion Implantation:

  • The process of adding impurities (B, P, As) to a silicon wafer. Adding impurities are also known as doping. (ni -> NA, ND).
  • The Impurities means ions are accelerated toward the wafer with the help of Electric Field and it tunnel into the crystal structure.
  • With the help of Lithography process, we can add these impurities selectively.


  • When we add the impurities into the wafer then it breaks the covalent bond of the structure. To improve/fix this damage, Annealing is the process.
  • Below figure helps you to understand.

 In the next part we will discuss about the various discuss different steps in the CMOS fabrication (Mostly only by Pictures).


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