Implant P+ Impurities: CMOS Processing (Part 5)
|Semiconductor Background||CMOS |
N-Well and Field Oxide
Gate Oxide and Poly Layer
Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different Article as per above table.
Let’s start where we have left in the last post (3D view of the wafer).
Few things are important (Few points are just copy paste from the previous post for better understanding.:) )
- This is the ideal process. In actual fabrication the Gate Length is affected. I have explained that in the last post. Please refer that.
- We are going to add Boron as part of P+ impurities. We can add other also.
- As a part of side effect of this process, resistance of poly decreases, Pfet threshold affected. But we are not going to discuss all these in this post.
- NMOS needs a body contact (which will be of p+ doping) the same as the Source(GND)
- PMOS needs a body contact (which will be of n+ doping) the same as the Drain (Vdd)
- From process and steps point of view, there is no difference while creating the NMOS and PMOS devices (except mask and the impurities). So we can interchange the steps (Means First we can create PMOS and then NMOS).
- In this we are going to create PMOS (Source and Drain) only. We are not creating the NMOS body contact (just because of space issue in the diagram) but the concept remains same as in case of PMOS body contact as we have discussed in the previous post.
Final 3D view of the Silicon Wafer is:
Till now we have created
- Active Region
- Channel Stop Region
- Field Oxide.
- Gate Oxide
- Poly layer.
- N+ regions (Source and Drain) for NMOS device.
- P+ regions (Source and Drain) for PMOS device.
In the next post we will talk about adding Metal Contact which will help us to pass the signal or data to MOS devices from the other MOS devices or from the External world.