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Monday, November 3, 2014

Implant N+ Impurities: CMOS Processing (Part 4)

Implant N+ Impurities:



Index Chapter1 Chapter2 Chapter3 Chapter4
Digital
Background
Semiconductor Background CMOS
Processing

3.1 3.2 3.3 3.4 3.5 3.6
Fabrication
Steps
Create
N-Well and Field Oxide
Create
Gate Oxide and Poly Layer
Implant
N+ Impurities
Implant
P+ Impurities
Create
Metal Contact

Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different articles as per above table.

Let’s start with the 3D diagram of silicon wafer where we left in the last post.



Final 2 diagram of last post is little bit small in size for clarifying the further processing. So again I am just expanding that and start the process from there on. :)



Now we will start the process of implant of Phosphorus (N type impurities), to create an N+ region in the P-type substrate. Final outcome of this will be the NMOS devices.

Few things are important here.
  • This is the ideal process. In actual fabrication the Gate Length is affected. I will explain with the diagram later in this post.
  • We are going to add Phosphorus as part of N impurities. We can add other also.
  • As a part of side effect of this process, resistance of poly decreases, Nfet threshold affected. But we are not going to discuss all these in this post.
  • NMOS needs a body contact (which will be of p+ doping) the same as the Source(GND)
  • PMOS needs a body contact (which will be of n+ doping) the same as the Drain (Vdd)
  • From process and steps point of view, there is no difference while creating the NMOS and PMOS devices (except mask and the impurities). So we can interchange the steps (Means First we can create PMOS and then NMOS).

Note:
  • In this post we will create the NMOS (Source and Drain) and PMOS body contact only.
  • Next post will be related to PMOS (Source and Drain) only. We are not creating the NMOS body contact (just because of space issue in the diagram ) but the concept remains same.



As I have mentioned that the channel length will be different, please understand with the help of below diagram. Same concept is going to apply for channel length in case of PMOS devices (which we will not discuss there).



Now the 3D view of the final silicon wafer is:



Till now we have created
  • Nwell
  • Active Region
  • Channel Stop Region
  • Field Oxide.
  • Gate Oxide
  • Poly layer.
  • N+ regions (Source and Drain) for NMOS device.

In the next post we will talk about adding P+ impurities which will help us to create PMOS devices.


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