## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Sunday, December 31, 2017

### Timing_sense : Timing Arc in .LIB Files (Part2)

 STA & SI:: Chapter 1: Introduction 1.1a 1.1b 1.1c 1.2a 1.2b INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

### Representation of The Unateness of timing Arc In timing Library:

In last article, we have discussed about the representation of Timing arc with respect to Logic gates in .lib file. In the Timing Library, "Timing Arc information" is stored with the syntax "timing_sense".

In this article, we are trying to extend timing arc concepts from simple "Logic gate" to complex combinational circuit. We will start with few standard logic functions like AOI (AND-OR-Inverter), OAI (OR-AND-Inverter). Then we will discuss about the few standard combinational circuits like MUX.

1) For Multiple Input and Single Output

AOI Gate: 3 Input and 1 Output: Y=((A.B)+C)'

To understand the circuit diagram and operation of AOI please refer Article AND-OR-Inverter

/* --------------- *
* Design : AOI21X1 *
* --------------- */
cell (AOI21X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.0179;
rise_capacitance : 0.0170;
fall_capacitance : 0.0173;
}

pin(B) {
direction : input;
capacitance : 0.0179;
rise_capacitance : 0.0174;
fall_capacitance : 0.0179;
}

pin(C) {
direction : input;
capacitance : 0.015;
rise_capacitance : 0.015;
fall_capacitance : 0.015;
}

pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.5;
function : "(!((A B)+C))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
.....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
.....
}
timing(C_Y) {
related_pin : "C";
timing_sense : negative_unate;
.....
}
....
}
.....
}

AOI Gate: 4 Input and 1 Output: Y=((A.B)+(C.D))'

/* -------------- *
* Design : AOI22X1 *
* -------------- */
cell (AOI22X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(C) {
direction : input;
....;
}
pin(D) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(!((A B)+(C D)))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
}
timing(C_Y) {
related_pin : "C";
timing_sense : negative_unate;
....
}
timing(D_Y) {
related_pin : "D";
timing_sense : negative_unate;
....
}
....
}
}

OAI Gate (OR-AND-Inverter): 4 Input and 1 Output: Y=((A+B)(C+D))'

/* -------------- *
* Design : OAI22X1 *
* -------------- */
cell (OAI22X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(C) {
direction : input;
....;
}
pin(D) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(!((A+B) (C+D)))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
}
timing(C_Y) {
related_pin : "C";
timing_sense : negative_unate;
....
}
timing(D_Y) {
related_pin : "D";
timing_sense : negative_unate;
....
}
....
}
}

Multiplexer: 2x1 MUX.

Multiplexer (2x1 MUX) has 2 Input pin, 1 Select pin and 1 output pin. Select pin is also a Input pin (whenever you see .lib file its very clearly defined as input pin). Now, we need to understand the relationship between different input and output pin. To understand this relationship, either you have internal circuit diagram or you can draw truth table or you can use the equation method. Let's see here with respect to equation.

MUX Input output equation is:
Y = (S'.A) + (S.B)

If you remember, previously we have discussed how you can figure out the unateness of output with respect to individual Input from equation (or say function) directly. Just in case, you want to revise, please check Unateness using Function Method.

From equation, it's clear that:
• Y is Positive Unate with respect to input pin A.
• Y is Positive Unate with respect to input pin B.
• Y is Non-unate with respect to Select line S.

Note: You can try other method your own. For more detail of these methods, please refer Article "Unateness in Complex Circuit".

Now, let's see .Lib representation of this.

/* -------------- *
* Design : MUX2X1 *
* -------------- */
cell (MUX2X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(S) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "((!S A) + (S B))";
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : positive_unate;
....
}
timing(S_Y) {
related_pin : "S";
timing_sense : non_unate;
....
}
....
}
}

Multiplexer: 2x1 MUX (Other configuration)

When I was checking the MUX with in the .Lib file, I come across another configuration. It's difficult to explain that here but with the help of equation you can easily figure out.

Y = ((S.A) + (S'.B))'

From this equation, you can easily say that
• Y is Negative Unate with respect to input pin A.
• Y is Negative Unate with respect to input pin B.
• Y is Non-unate with respect to Select line S.

Now, .lib representation is also very clear. :) Only Output Y section

pin(Y) {
direction : output;
....;
function : "(!((S A) + (!S B)))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
}
timing(S_Y) {
related_pin : "S";
timing_sense : non_unate;
....
}
....
}

2) For Multiple Input and Multiple Output

You might be thinking about any logic gates having multiple output. I would say forget about that and try to understand how to represent such circuit in .LIB file. Below are 2 output function which I can see in my .lib file (Snapshot of .LIB which I have) for a particular CELL.

YC = ((A B)+(B C))+(C A) &
YS = (A^B)^C

Note: I am sure after seeing Equation, you must have figured out the circuit I am talking about. :) Yes, It's a Fully Adder Circuit. Similarly, you can have Half Added Circuit as part of your Library. :)

/* -------------- *
* Design : FAX1 *
* -------------- */
cell (FAX1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(C) {
direction : input;
....;
}
pin(YC) {
direction : output;
....;
function : "(((A B)+(B C))+(C A))";
timing(A_YC) {
related_pin : "A";
timing_sense : positive_unate;
....
}
timing(B_YC) {
related_pin : "B";
timing_sense : positive_unate;
....
}
timing(C_YC) {
related_pin : "C";
timing_sense : positive_unate;
....
}
....
}

pin(YS) {
direction : output;
....;
function : "((A^B)^C)";
timing(A_YC) {
related_pin : "A";
timing_sense : non_unate;
....
}
timing(B_YC) {
related_pin : "B";
timing_sense : non_unate;
....
}
timing(C_YC) {
related_pin : "C";
timing_sense : non_unate;
....
}
....
}
}

I am sure, by now you are very much clear about the representation of Unateness in .LIB file for all logic gates and few Standard combinational circuit. Any circuit which is similar to this, you can easily understand the input-output relationship just by seeing these few (direction, related_pin, function, timing_sense) parameters in the .Lib file. Or you can write any .lib file if you already have input-output relationship.

Now, there are few special Cells like TriState Cell (e.g TriState Buffer) and Sequential Cells like D flipflop which are still untouched in our discussion. For that we have to introduce few new parameters as a part of Timing Arc. Let's discuss those in next articles.

Happy Learning

### Timing_sense : Timing Arc in .LIB Files (Part1)

 STA & SI:: Chapter 1: Introduction 1.1a 1.1b 1.1c 1.2a 1.2b INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

### Representation of The Unateness of timing Arc In timing Library:

In the Timing Library, "Timing Arc information" is stored with the syntax "timing_sense".

1) For Single Input and Single Output

Buffer : timing_sense: positive_unate

/* --------------- *
* Design : BUF2X1 *
* --------------- */
cell (buf){
....
pin (A) {
....
direction : input;
capacitance : 1.0;
} /* End pin (A) */

pin(Y){
direction : output;
capacitance : 0.0;
function : "(A)";
....
....
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
....
....
}
...
...
}/* End pin (Y) */
}/* End cell (buf) */

So basically "timing_sense" will represent the unateness of a particular pin. But remember, if you wants to know the number of Timing Arc - then it's 2. One for Falling edge and other for Rising Edge.

Inverter : timing_sense: negative_unate

/* --------------- *
* Design : INVX1 *
* --------------- */
cell (inv){
....
pin (A) {
....
direction : input;
capacitance : 1.0;
} /* End pin (A) */

pin(Y){
direction : output;
capacitance : 0.0;
function : "(!A)";
....
....
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
....
}
...
...
}/* End pin (Y) */
}/* End cell (inv) */

Note:
• If you have noticed (or If you will compare in .lib file), through most of the parameters it's very difficult to understand whether it's Buffer or Inverter. There are only 2 parameter which can help you: "function" and "timing_sense".
• Name inside the timing() - is the Timing Arc name.
• You can see (in above examples) there is 1 Input Pin - which is A and one Output Pin which is Y. Now timing() is "related to" output Pin Y because timing arc is attached to an output pin. (you can get more clarity on this point later in this article)

2) For Multiple Input and Single Output

AND gate: timing_sense: positive_unate

To know more about the Unateness of AND gate, please read Article "Unateness- Timing Arc: AND gate"
/* --------------- *
* Design : AND2X1 *
* --------------- */
cell (AND2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.5;
function : "(A B)";
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
.....
.....
}
timing(B_Y) {
related_pin : "B";
timing_sense : positive_unate;
.....
.....
}
....
....
}
.....
.....
}

In this case both the Pins are of same type, we can combine the definition of timing arc into one. Like
timing(A_Y, B_Y) {
related_pin : "A B";
timing_sense : positive_unate;
....
....
}

Remember, all the parameters should be same. There are few parameters which we haven't discuss till now, but in reality before combining we have to review all.

OR gate: timing_sense: positive_unate

To know more about the Unateness of OR Gate, please read Article "Unateness- Timing Arc: OR Gate"
/* -------------- *
* Design : OR2X1 *
* -------------- */
cell (OR2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.015;
rise_capacitance : 0.015;
fall_capacitance : 0.015;
}
pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.4;
function : "(A+B)";
timing(A_Y) {
related_pin : "A";
timing_sense : positive_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : positive_unate;
....
....
}
....
....
}
}

NOR gate: timing_sense: negative_unate

To know more about the Unateness of NOR gate, please read Article "Unateness- Timing Arc: NOR gate"
/* -------------- *
* Design : NOR2X1 *
* -------------- */
cell (NOR2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.015;
rise_capacitance : 0.015;
fall_capacitance : 0.015;
}
pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}
pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.4;
function : "(!(A+B))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
....
....
}
....
....
}
}

NAND gate: timing_sense: negative_unate

To know more about the Unateness of NAND gate, please read Article "Unateness- Timing Arc: NAND gate"
/* --------------- *
* Design : NAND2X1 *
* --------------- */
cell (NAND2X1) {
....
....
pin(A) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(B) {
direction : input;
capacitance : 0.01;
rise_capacitance : 0.01;
fall_capacitance : 0.01;
}

pin(Y) {
direction : output;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 0.5;
function : "(!(A B))";
timing(A_Y) {
related_pin : "A";
timing_sense : negative_unate;
.....
.....
}
timing(B_Y) {
related_pin : "B";
timing_sense : negative_unate;
.....
.....
}
....
....
}
.....
.....
}

XNOR gate: timing_sense: non_unate

To know more about the Unateness of XNOR gate, please read Article "Unateness- Timing Arc: XNOR gate"
/* -------------- *
* Design : XNOR2X1 *
* -------------- */
cell (XNOR2X1) {
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(!(A^B))";
timing(A_Y) {
related_pin : "A";
timing_sense : non_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : non_unate;
....
....
}
....
}
}

XOR gate: timing_sense: non_unate

To know more about the Unateness of XOR gate, please read Article "Unateness- Timing Arc: XOR gate"
/* -------------- *
* Design : XOR2X1 *
* -------------- */
cell (XOR2X1) {
....
....
pin(A) {
direction : input;
....;
}
pin(B) {
direction : input;
....;
}
pin(Y) {
direction : output;
....;
function : "(A^B)";
timing(A_Y) {
related_pin : "A";
timing_sense : non_unate;
....
....
}
timing(B_Y) {
related_pin : "B";
timing_sense : non_unate;
....
....
}
....
}
}

Representation of Unateness for few more complex circuits (like MUX) and Sequential circuits, we will discuss in next Articles.

## Monday, December 25, 2017

### Single VIA, VIA array, Stacked VIA

A via forms a connection between overlapping geometries on different layers through a cut layer, and is formed by geometries on all three layers.
Three types of vias:
1. a single via,
2. an array via,
3. and a stacked via.

### 1) Single VIA

Below diagram help you to understand how single VIA are placed between 2 metal and help them to connect them.
2D /Top view with different arrangement (also known as Layout View)

Figure 3D_b is a transparent view of the 3D_a. It helps you to understand how different layers are connected with each other.

Side View of Via and Metal connection.

There are certain Design rules for VIAs also. I am not going to capture those in detail here but below figure give you a general idea.

Vias can be asymmetric, meaning the overhangs in the x and y directions are different. The overhang parameters refer to those of a via connecting preferred-direction wires. If the wires are in the nonpreferred direction, the via is rotated and the overhangs are reversed, meaning that the extensions in the x direction are given by the y overhang parameters.

### 2) VIA Array

Array vias are used for connecting wide wires where the required cut size would exceed the maximum cut size of the simple via. In an array via, the region of intersection of the wires is filled by a regular array of small cuts of fixed size and separation.

2D /Top view with and without preferred direction of Metal arrangement (also known as Layout View)

Figure 3D_b is a transparent view of the 3D_a. It helps you to understand how different layers are connected with each other. you can also see that array size is 3x1 between M1 and M2. When it comes to M2 and M3, Single VIA connects both the wire. But dnt think that it will always be the case. It depends on design that and width of Metal wire, if you want to use VIA array or Single VIA. In the below figure, you can see that M1 and M2 are using 3x3 VIA array. Between M2 and M3 - it's 1x3 VIA array.

### 3) Stack VIA

2D view of Stack via is not easy to understand. But if you want to try, you can do it in any tool to understand properly.

I can summarize this article with combined view of all 3 type of VIAs.

## Monday, November 27, 2017

### Metal Wire Orientation (HVH or VHV)

In previous articles, we have discussed a lot about type of metal wire like Mx, My and others. We have also discussed about the Metal stack like 6 Metal layer stack : M1_3Mx_My_Mz. (If you have confusion, please refer Article "Metal Layer Stack Nomenclature").

In this article, we are going to understand another important concept: "Metal layer Orientation". Actually during routing of design, we use a terminology "Preferred Routing Direction" of Metal layer. May be you have heard HVH or VHV routing strategy. Even if not - then I am sure you have seen below fig somewhere :) .

In the above pic, you can see that M1, M3 & M5 are in Horizontal direction and M2 & M4 are in vertical direction. Still confused ??? :) Let me help you.

Metal wires in our design are at different levels. If, I assume that M1 is at first level then M2 is at second level, M3 at third and so on. Type of Metal (Mx, My, Mz) depends as per Metal Stack you are going to choose for your design. (For more detailing about the Metal stack - please refer Article "Metal Layer Stack"). By now, you should be clear that different metals present at different height with respect to substrate.

Now, only one question is remaining, how we are going to route these metals? How in the sense - in which direction or say orientation. Is/are there any standard/s behind this or user can route these metals wires as per their requirement? Very short answer of this question - There are standards or say recommendation for routing Metal wires. Timing is very critical now a days. From metal wires point of view - capacitance between them plays a very important role. (Note: Delay has relationship with RC constant - and this C is because of Capacitance between the wires). So as a designer we have to understand or say use those technique which can minimize these unwanted Capacitance (Remember - capacitance between Wires are always unwanted. It's always has side effect in negative sense :) ). To understand different type of capacitance between wires, you can refer Article "Basic of Capacitance & Resistance (from VLSI Point of view)"

Capacitance between 2 plates depends on area of plates parallel to each other OR I can say overlap area between 2 metal wires. During Routing - there are 2 extreme routing methodology.
1. Parallel Routing Grid
2. Cross Routing Grid

If we place metal wire on these routing grids (as an example - just picked only 2 wires of same metal layer), you can easily understand the concept of overlap area. Remember, right now we are talking about Ground cap (or Area cap) and not Coupling cap.

Parallel Metal Wire Orientation:

In the below figure, I have tried to show arrangement of capacitance between parallel metal wire between metal layers of different levels Like capacitance between M1 and M2. Since M1 and M2 both are parallel to each other 100%, Capacitance between them has dependency on width and length of the wire. This arrangement gives maximum Ground cap (Area cap).
Note: We are not discussing the capacitance between same type of metal layers (Between M1 and M1) known as Coupling Capacitance.

Cross / Perpendicular Metal Wire Orientation:

In the below figure, you can see that overlap area between M1 and M2 is only at their cross-section. This overlap area depends on their corresponding width parameter. You can see that their is no dependency on length of the wire. This arrangement gives minimum Ground cap (Area cap).
Front view and Side view of this arrangement helps you to understand this routing methodology more closely.

You can see that if we want to reduce the CAP then orientation of the Metal wire is very important. Cross (perpendicular) metal wire orientation gives minimum capacitance and that's the reason it's recommended. One of the direction is considered as Horizontal and other as Vertical. That's the reason - these orientation is known as HVH or VHV orientation (and corresponding routing strategy as HVH or VHV routing methods).

## Saturday, November 25, 2017

### Delay Interview Questions (Part 2)

In the last part (Delay Interview Questions: Part 1), we have discusses 2 scenarios
1. Min & Max Delay Between 2 points having multi-paths when Delay are given as absolute number.
2. Min & Max Delay between 2 points having multi-paths when Delay are given as Rise and Fall delay.
We have discussed these concepts from Interview point of view.
Note: Example 1 and Example 2, we have already discussed in last article.

### Example 3:

Note: Above figure is same as in Example 1 and Example 2 (with small addition).

All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay:
Arc a1 -> y1 = (1.25ns, 1.5ns)
Arc b1 -> y1 = (1.1ns, 1.9ns)
OR gate (min, max) delay:
Arc a2 -> y2 = (0.3ns, 0.4ns)
Arc b2 -> y2 = (0.5ns, 0.9ns)

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
This question is almost equal to the example 1 but with slight modification. Now, we are talking about the different input and output combination of AND gate. Remember, every input and output combination has it's own delay value. When we talk about the Delay of a Gate and if it's not related to input and output combination, it means we are talking about Boundaries of overall gate delay. To understand this concept - you need to revise or say understand Timing Arc concepts. Please read article Timing Arc and Unate: Timing Arc.

Intension of this question is to get more accurate delay value based on Path base analysis.
Note: Delay calculation in such circuit are of 2 type - Path base Analysis and Graph Base Analysis. You can get more detail about this in Article - Path Base Vs Graph Base Analysis: Part 1.

There is a little bit change in the picture of Path 1 and Path 2 (in compare to Example 1 and Example 2).

In the above figure, you can see that
Path 1: Q1 -> Inverter -> b1 -> y1 -> Buffer -> a2 -> y2 -> Buffer -> D2
Path 2: Q1 -> Inverter -> Inverter -> Inverter -> b2 -> y2 -> Buffer -> D2

In Path 1:
b1 -> y1 is basically part of AND gate and during delay calculation we will use delay value as per Arc b1 -> y1 = (1.1ns, 1.9ns).
a2 - > y2 is basically part of OR gate and delay values are as per Arc a2 -> y2 = (0.3ns, 0.4ns).

In Path 2:
b2 - > y2 is basically part of OR gate and delay values are as per Arc b2 -> y2 = (0.5ns, 0.9ns).

Solution:
Path 1 (Min Delay) : 0.25 (inverter) + 1.1 (b1 -> y1) + 0.1 (buffer) + 0.3 (a2 -> y2) + 0.1 (buffer) = 1.85ns
Path 1 (Max Delay) : 1.00 (inverter) + 1.9 (b1 -> y1) + 0.2 (buffer) + 0.4 (a2 -> y2) + 0.2 (buffer) = 3.70ns

Path 2 (Min Delay) : 0.25 (inverter) + 0.25 (inverter) + 0.25 (inverter) + 0.5 (b2 -> y2) + 0.1 (buffer) = 1.35ns
Path 2 (Max Delay) : 1.00 (inverter) + 1.0 (inverter) + 1.0 (inverter) + 0.9 (b2 -> y2) + 0.2 (buffer) = 4.1ns

Overall Min Delay between Q1 and D2 = 1.35ns (From Path 2)
Overall Max Delay between Q1 and D2 = 4.1ns (From Path 2)

### Example 4:

All Buffer has same delay:
Tphl (min, max) = (0.1ns, 0.18ns)
Tplh (min, max) = (0.15ns, 0.20ns)
All NOT Gate has same delay:
Tphl (min, max) = (0.25ns, 0.75ns)
Tplh (min, max) = (0.5ns, 1.0ns)
AND gate delay:
Arc a1 -> y1:
Tphl (min, max) = (1.25ns, 1.5ns)
Tplh (min, max) = (1.3ns, 1.75ns)
Arc b1 -> y1
Tphl (min, max) = (1.0ns, 1.9ns)
Tplh (min, max) = (1.1ns, 2.0ns)
OR gate (min, max) delay:
Arc a2 -> y2:
Tphl (min, max) = (0.3ns, 0.35ns)
Tplh (min, max) = (0.31ns, 0.4ns)
Arc b2 -> y2:
Tphl (min, max) = (0.51ns, 0.9ns)
Tplh (min, max) = (0.5ns, 0.75ns)

Note:
Tphl = Propagation Delay High to Low
Tplh = Propagation Delay Low to High

Question: Find out the Tplh and Tphl at point D2 with respect to Input Q1?

Explanation:
For this you need to understand the concepts of Tphl and Tplh. I am assuming that you know this part. Here we have to understand how different waveform (Rising input or Falling input) is going to behave in this circuit.

There is a little bit change in the picture of Path 1 and Path 2 (in compare to Example 1 and Example 2).

We have to do 2 type of analysis for each path - Rising & Falling signal analysis at D1 for both paths.

Rising Signal Analysis (For Path1):
• Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• AND gate is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of AND gate for ARC b1 -> y1 => (1.0ns, 1.9ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)
• OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of OR gate for ARC a2 -> y2 => (0.3ns, 0.35ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)

For Rising Signal at the Input (Q1), we are getting Falling Signal at the Output (D2) through Path1. So in this scenario, delay between Q1 and D1 through Path1 = Tphl.
Minimum Tphl at D1 through Path 1 = 0.25ns + 1.0ns + 0.1ns + 0.3ns + 0.1ns = 1.75ns
Maximum Tphl at D1 through Path 1 = 0.75ns + 1.9ns + 0.18ns + 0.35ns + 0.18ns = 3.36ns

Falling Signal Analysis (For Path1):
• Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• AND gate is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of AND gate for ARC b1 -> y1 => (1.1ns, 2.0ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)
• OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of OR gate for ARC a2 -> y2 => (0.31ns, 0.4ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)

For Falling Signal at the Input (Q1), we are getting Rising Signal at the Output (D2) through Path1. So in this scenario, delay between Q1 and D1 through Path1 = Tplh.
Minimum Tplh at D1 through Path 1 = 0.5ns + 1.1ns + 0.15ns + 0.31ns + 0.15ns = 2.21ns
Maximum Tplh at D1 through Path 1 = 1.0ns + 2.0ns + 0.20ns + 0.40ns + 0.20ns = 3.80ns

Rising Signal Analysis (For Path2):
• Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of OR gate for ARC b2 -> y2 => (0.51ns, 0.9ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)

For Rising Signal at the Input (Q1), we are getting Falling Signal at the Output (D2) through Path2. So in this scenario, delay between Q1 and D1 through Path2 = Tphl.
Minimum Tphl at D1 through Path 2 = 0.25ns + 0.5ns + 0.25ns + 0.51ns + 0.10ns = 1.61ns
Maximum Tphl at D1 through Path 2 = 0.75ns + 1.0ns + 0.75ns + 0.90ns + 0.18ns = 3.58ns

Falling Signal Analysis (For Path2):
• Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of OR gate for ARC b2 -> y2 => (0.5ns, 0.75ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)

For Falling Signal at the Input (Q1), we are getting Rising Signal at the Output (D2) through Path2. So in this scenario, delay between Q1 and D1 through Path2 = Tplh.
Minimum Tplh at D1 through Path 2 = 0.50ns + 0.25ns + 0.50ns + 0.50ns + 0.15ns = 1.90ns
Maximum Tplh at D1 through Path 2 = 1.00ns + 0.75ns + 1.00ns + 0.75ns + 0.20ns = 3.70ns

Solution:
Through Path 1 (Min Tplh) : 2.21ns
Through Path 1 (Min Tphl) : 1.75ns

Through Path 2 (Min Tplh) : 1.90ns
Through Path 2 (Min Tphl) : 1.61ns

Through Path 1 (Max Tplh) : 3.80ns
Through Path 1 (Max Tphl) : 3.36ns

Through Path 2 (Max Tplh) : 3.70ns
Through Path 2 (Max Tphl) : 3.58ns

Overall Minimum Tplh at D2 (when input is at Q1) = 1.90ns (Through Path 2)
Overall Maximum Tplh at D2 (when input is at Q1) = 3.80ns (Through Path 1)
Overall Minimum Tphl at D2 (when input is at Q1) = 1.61ns (Through Path 2)
Overall Maximum Tphl at D2 (when input is at Q1) = 3.58ns (Through Path 2)

In Summary, I can write, At D2 with respect to Q1 Tphl = (1.61ns, 3.58ns) & Tplh = (1.90ns, 3.80ns)

Is it done? I mean do you think Interviewer is going to stop at this point. :) :) Don't ever think. By now they will realize that you are good in below concepts.
• Min and Max Delay Calculation
• Delay calculation based on Timing Arc (I can say some part of Path base & Graph base analysis)
• Tphl and Tplh based Delay Calculation
• Multipath Delay Calculation
• Use of Rising edge and Falling Edge at Input during delay calculation

Now, it's time to check few more concepts related to CELL Delay (Like Cell Delay as a function of Input Transition Vs Output Load) and then how you can use those concepts in delay calculation of Combinational Circuit. :) Lets discuss this in Next Article.

## Tuesday, November 7, 2017

### Path Base Analysis (PBA) Vs Graph Base Analysis (GBA) - part1

Today, we are going to discuss about the Path base analysis Vs Graph base analysis. As such difference is more complex compare to what I am going to explain, but right now it's sufficient to start with. :)

Let's you have a combinational path with Net delay (min, max) and Cell delay (As per the Timing Arc). If, you have any confusion with respect to the timing arc, please refer below articles.
In the below figure, you can see AND gate (1) has 2 input, so 2 set of input-output delay combination.
• Min Delay = 0.5ns, Max Delay = 1.5ns
• Min Delay = 0.2ns, Max Delay = 1.2ns
Similarly, for other logic gates.

Now, if I will ask you to calculate the delay between point A and point B, then the concept of PBA and GBA comes into the picture. Before, I explain you this concept, please refer below few figures and then see the difference between PBA and GBA.

I am sure, if you have notice closely, then you have already realized the difference. :) But still let me highlight that.

In GBA (Graph Base Analysis), in place of choosing 2 combinations of AND gate (1) delay, i.e. (Combination_1: 0.5ns, 1.5ns ; Combination_2: 0.2ns, 1.2ns) we choose extreme boundaries, i.e. min delay = 0.2ns and max delay = 1.5ns.

In case of PBA (Path base Analysis), we are using actual delay between input pin and output combination (means choosing both combination of delay).
• Combination_1: 0.5ns, 1.5ns
• Combination_2: 0.2ns, 1.2ns

Note: Check the similar difference for AND gate (2) also.

You might be thinking that this is not accurate (means why in GBA we missed 2 value), we are adding unnecessary delay in our calculation. And I am glad to say that you are right. :) The reason we are doing this because from tool point of view - doing analysis or say calculation as per GBA is very fast compare to PBA. Runtime of tool is very low. And only difference is that we are adding pessimism in our calculation.

Now, if you want to understand the calculation of delay between different input pin (A, B, C) and Output Pin (Y), please check below figures.

Note: For clarity purpose (used different color combination) - I did this calculation and pasting in the form of picture. :)

Delay Calculation in Case of GBA (Graph base Analysis).

Delay Calculation in Case of PBA (Path base Analysis).

Important observation, which you all should noticed:

Delay between A and Y
Graph base analysis (Min, Max) : 7.25ns, 10.35ns
Path base analysis (Min, Max) : 7.55ns, 10.10ns

You can see that delay between A and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA < min_delay_in_PBA
max_delay_in_GBA > max_delay_in_PBA

Delay between B and Y
Graph base analysis (Min, Max) : 7.75ns, 10.85ns
Path base analysis (Min, Max) : 7.75ns, 10.30ns

You can see that delay between B and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA = min_delay_in_PBA
max_delay_in_GBA > max_delay_in_PBA

Delay between C and Y
Graph base analysis (Min, Max) : 7.05ns, 9.05ns
Path base analysis (Min, Max) : 7.25ns, 9.05ns

You can see that delay between A and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA < min_delay_in_PBA
max_delay_in_GBA = max_delay_in_PBA

Let me summarize whole concept:
min_delay_in_GBA <= min_delay_in_PBA
max_delay_in_GBA >= max_delay_in_PBA

Now, everything is good but still you may have confusion or question - why GBA? Because from above calculation, it's not clear how it's going to save Analysis Time of a Tool. How it's beneficial for Industry? If you have all these questions, no need to worry, I will explain but not in this article. I will do that next time. But I can give you hint, so that you can think about this once.
Hint:
1) Check how these minimum and maximum delays are calculated?
2) Adding Pessimism is not an problem, it's just margin in your delay calculation. How adding margin can help us?
3) What all different environment or other factors or parameters you have to consider while calculating Delay based on different timing Arc of a gate?

I think, for now, these hints are good enough. Comment here - if you know the Answer of this, else wait for next related article. :)

BEST OF LUCK.
By - Puneet Mittal
(Founder of VLSI-Expert Group)
PBA)

## Monday, October 30, 2017

### Background of Types of Dielectric layer

Dielectric layers are of 2 types.
1. Planar Dielectric
2. Conformal Dielectric

Planar Dielectric:

All Dielectric in the below figure (D1 to D7) are Planar dielectric.

Conformal Dielectric:

Different type of Conformal dielectric structures are shown in below figure. There are certain parameters which helps to identify any conformal dielectric like Side thickness, Bottom thickness or Top thickness.

### Modelling of Dielectric in Technology File

Modelling of Dielectric layer in technology file vary as per extraction software or you can say that as per EDA vendor. Different EDA vendor uses different ways to represents this as per their requirement. Even if I know their syntax, I can't write here. :) But what I am going to do - explain everything in more easy language. :) Once you start working, you can check their manual and try to map my syntax with their syntax. :)

To represent a Planar Dielectric (Non-Conformal) we need to have following basic information.

(Parameter Name : my_nomenclature )
Dielectric constant : di_constant
Thickness : thickness
Height from the Substrate : height
Name of Dielectric : DIELECTRIC
Type of Dielectric : conformal=false

To represent a Conformal Dielectric we need to have following extra information.

(Parameter Name : my_nomenclature )
Side Thickness : S_thickness
Bottom Thickness : B_thickness
Top Thickness : T_thickness
Type of Dielectric : conformal=true
Parent Layer : p_layer (This is the layer around which dielectric is present. It can be a conductor like Poly, Metal1 or may be any other Dielectric also. In above figure, M1 is the Parent layer).

Planar Dielectric

Modelling in Technology file:

DIELECTRIC DEL2
di_constant = 4.8
thickness = 2.7
height = 4.1
conformal = false

DIELECTRIC DEL3
di_constant = 2.8
thickness = 0.3
height = 6.8
conformal = false

Conformal Dielectric

There are different scenarios which need to understand. These scenarios are same as we have discussed in the article of Conformal Dielectric (It will help you to map easily)

### Scenario 1:

Modelling in Technology file:

DIELECTRIC DEL_M1a
conformal = true
T_thickness = 0.2
S_thickness = 0.2
B_thickness = 0
di_constant = 3.8
thickness = 0
height = 4.1
p_layer = M1

DIELECTRIC DEL_M1b
conformal = true
T_thickness = 0
S_thickness = 0.2
B_thickness = 0.2
di_constant = 3.8
thickness = 0
height = 4.1
p_layer = M1

### Scenario 2:

Modelling in Technology file:

DIELECTRIC DEL_a
conformal = true
T_thickness = 0.2
S_thickness = 0
B_thickness = 0
di_constant = 3.8
thickness = 0
height = 4.1
p_layer = M1

DIELECTRIC DEL_b
conformal = true
T_thickness = 0
S_thickness = 0.2
B_thickness = 0
di_constant = 3.8
thickness = 0
height = 4.1
p_layer = M1

DIELECTRIC DEL_c
conformal = true
T_thickness = 0
S_thickness = 0
B_thickness = 0.2
di_constant = 3.8
thickness = 0
height = 4.1
p_layer = M1

### Scenario 3:

Representation of DEL_a1, DEL_a2 and DEL_a3 in Technology file:

DIELECTRIC DEL_a1
conformal = true
T_thickness = 0.2
S_thickness = 0
B_thickness = 0
di_constant = 3.8
thickness = 0
height = 4.1
p_layer = M1

DIELECTRIC DEL_a2
conformal = true
T_thickness = 0.15
S_thickness = 0
B_thickness = 0
di_constant = 2.8
thickness = 0
height = 4.1
p_layer = DEL_a1

DIELECTRIC DEL_a3
conformal = true
T_thickness = 0.15
S_thickness = 0
B_thickness = 0
di_constant = 1.8
thickness = 0
height = 4.1
p_layer = DEL_a2

Remember: In above representation, for DEL_a2, p_layer is previous dielectric (i.e DEL_a1). It's because this dielectric has parent layer DEL_a1. It's deposited on the top of DEL_a1. Top thickness also measured with respect to DEL_a1.
Note: you might be thinking why Height parameter is same in all 3 cases. It depends on EDA vendor, how they want to represent the height of Conformal layer. Here I am assuming that my tool is going to automatically measure actual height with the help of provided data. :)

Representation of DEL_b1 and DEL_b2 in Technology file:

DIELECTRIC DEL_b1
conformal = true
T_thickness = 0
S_thickness = 0.2
B_thickness = 0
di_constant = 3.8
thickness = 0
height = 4.1
p_layer = M1

DIELECTRIC DEL_b2
conformal = true
T_thickness = 0
S_thickness = 0.15
B_thickness = 0
di_constant = 2.8
thickness = 0
height = 4.1
p_layer = DEL_b1

Similarly, Representation of DEL_c1 and DEL_c2 in Technology file:

DIELECTRIC DEL_c1
conformal = true
T_thickness = 0
S_thickness = 0
B_thickness = 0.2
di_constant = 3.8
thickness = 0
height = 4.1
p_layer = M1

DIELECTRIC DEL_c2
conformal = true
T_thickness = 0
S_thickness = 0
B_thickness = 0.15
di_constant = 2.8
thickness = 0
height = 4.1
p_layer = DEL_c1

### Scenario 4:

Modelling in Technology file:

DIELECTRIC DEL2
conformal = true
T_thickness = 0.1
S_thickness = 0.2
B_thickness = 0.0
di_constant = 2.8
thickness = 0.4
height = 4.1
p_layer = M1

DEL2 is a conformal dielectric & the reason behind this is - It has a Side Thickness and Top thickness parameter. But you may be thinking that it looks like a planar at all other places, it's shape is similar to non-conformal dielectric. I can understand your confusion. Actually, you are right that at certain places it's conformal and at some places it's non-conformal.
In the representation of all conformal layer, you may have noticed that thickness parameter is 0. It's because they dnt have any thickness as such (I am not talking about top thickness. That's a different parameter). In this case, this thickness parameter is non-zero like in case of Planar dielectric.

At the end, I just wanted to highlight once again that different EDA vendors have different syntax and different way to represent dielectric layers in technology file. Above representation is just for your understanding purpose, it's not specific to any company.