## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Saturday, November 25, 2017

### Delay Interview Questions (Part 2)

In the last part (Delay Interview Questions: Part 1), we have discusses 2 scenarios
1. Min & Max Delay Between 2 points having multi-paths when Delay are given as absolute number.
2. Min & Max Delay between 2 points having multi-paths when Delay are given as Rise and Fall delay.
We have discussed these concepts from Interview point of view.
Note: Example 1 and Example 2, we have already discussed in last article.

### Example 3:

Note: Above figure is same as in Example 1 and Example 2 (with small addition).

All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay:
Arc a1 -> y1 = (1.25ns, 1.5ns)
Arc b1 -> y1 = (1.1ns, 1.9ns)
OR gate (min, max) delay:
Arc a2 -> y2 = (0.3ns, 0.4ns)
Arc b2 -> y2 = (0.5ns, 0.9ns)

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
This question is almost equal to the example 1 but with slight modification. Now, we are talking about the different input and output combination of AND gate. Remember, every input and output combination has it's own delay value. When we talk about the Delay of a Gate and if it's not related to input and output combination, it means we are talking about Boundaries of overall gate delay. To understand this concept - you need to revise or say understand Timing Arc concepts. Please read article Timing Arc and Unate: Timing Arc.

Intension of this question is to get more accurate delay value based on Path base analysis.
Note: Delay calculation in such circuit are of 2 type - Path base Analysis and Graph Base Analysis. You can get more detail about this in Article - Path Base Vs Graph Base Analysis: Part 1.

There is a little bit change in the picture of Path 1 and Path 2 (in compare to Example 1 and Example 2).

In the above figure, you can see that
Path 1: Q1 -> Inverter -> b1 -> y1 -> Buffer -> a2 -> y2 -> Buffer -> D2
Path 2: Q1 -> Inverter -> Inverter -> Inverter -> b2 -> y2 -> Buffer -> D2

In Path 1:
b1 -> y1 is basically part of AND gate and during delay calculation we will use delay value as per Arc b1 -> y1 = (1.1ns, 1.9ns).
a2 - > y2 is basically part of OR gate and delay values are as per Arc a2 -> y2 = (0.3ns, 0.4ns).

In Path 2:
b2 - > y2 is basically part of OR gate and delay values are as per Arc b2 -> y2 = (0.5ns, 0.9ns).

Solution:
Path 1 (Min Delay) : 0.25 (inverter) + 1.1 (b1 -> y1) + 0.1 (buffer) + 0.3 (a2 -> y2) + 0.1 (buffer) = 1.85ns
Path 1 (Max Delay) : 1.00 (inverter) + 1.9 (b1 -> y1) + 0.2 (buffer) + 0.4 (a2 -> y2) + 0.2 (buffer) = 3.70ns

Path 2 (Min Delay) : 0.25 (inverter) + 0.25 (inverter) + 0.25 (inverter) + 0.5 (b2 -> y2) + 0.1 (buffer) = 1.35ns
Path 2 (Max Delay) : 1.00 (inverter) + 1.0 (inverter) + 1.0 (inverter) + 0.9 (b2 -> y2) + 0.2 (buffer) = 4.1ns

Overall Min Delay between Q1 and D2 = 1.35ns (From Path 2)
Overall Max Delay between Q1 and D2 = 4.1ns (From Path 2)

### Example 4:

All Buffer has same delay:
Tphl (min, max) = (0.1ns, 0.18ns)
Tplh (min, max) = (0.15ns, 0.20ns)
All NOT Gate has same delay:
Tphl (min, max) = (0.25ns, 0.75ns)
Tplh (min, max) = (0.5ns, 1.0ns)
AND gate delay:
Arc a1 -> y1:
Tphl (min, max) = (1.25ns, 1.5ns)
Tplh (min, max) = (1.3ns, 1.75ns)
Arc b1 -> y1
Tphl (min, max) = (1.0ns, 1.9ns)
Tplh (min, max) = (1.1ns, 2.0ns)
OR gate (min, max) delay:
Arc a2 -> y2:
Tphl (min, max) = (0.3ns, 0.35ns)
Tplh (min, max) = (0.31ns, 0.4ns)
Arc b2 -> y2:
Tphl (min, max) = (0.51ns, 0.9ns)
Tplh (min, max) = (0.5ns, 0.75ns)

Note:
Tphl = Propagation Delay High to Low
Tplh = Propagation Delay Low to High

Question: Find out the Tplh and Tphl at point D2 with respect to Input Q1?

Explanation:
For this you need to understand the concepts of Tphl and Tplh. I am assuming that you know this part. Here we have to understand how different waveform (Rising input or Falling input) is going to behave in this circuit.

There is a little bit change in the picture of Path 1 and Path 2 (in compare to Example 1 and Example 2).

We have to do 2 type of analysis for each path - Rising & Falling signal analysis at D1 for both paths.

Rising Signal Analysis (For Path1):
• Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• AND gate is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of AND gate for ARC b1 -> y1 => (1.0ns, 1.9ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)
• OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of OR gate for ARC a2 -> y2 => (0.3ns, 0.35ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)

For Rising Signal at the Input (Q1), we are getting Falling Signal at the Output (D2) through Path1. So in this scenario, delay between Q1 and D1 through Path1 = Tphl.
Minimum Tphl at D1 through Path 1 = 0.25ns + 1.0ns + 0.1ns + 0.3ns + 0.1ns = 1.75ns
Maximum Tphl at D1 through Path 1 = 0.75ns + 1.9ns + 0.18ns + 0.35ns + 0.18ns = 3.36ns

Falling Signal Analysis (For Path1):
• Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• AND gate is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of AND gate for ARC b1 -> y1 => (1.1ns, 2.0ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)
• OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of OR gate for ARC a2 -> y2 => (0.31ns, 0.4ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)

For Falling Signal at the Input (Q1), we are getting Rising Signal at the Output (D2) through Path1. So in this scenario, delay between Q1 and D1 through Path1 = Tplh.
Minimum Tplh at D1 through Path 1 = 0.5ns + 1.1ns + 0.15ns + 0.31ns + 0.15ns = 2.21ns
Maximum Tplh at D1 through Path 1 = 1.0ns + 2.0ns + 0.20ns + 0.40ns + 0.20ns = 3.80ns

Rising Signal Analysis (For Path2):
• Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of OR gate for ARC b2 -> y2 => (0.51ns, 0.9ns)
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)

For Rising Signal at the Input (Q1), we are getting Falling Signal at the Output (D2) through Path2. So in this scenario, delay between Q1 and D1 through Path2 = Tphl.
Minimum Tphl at D1 through Path 2 = 0.25ns + 0.5ns + 0.25ns + 0.51ns + 0.10ns = 1.61ns
Maximum Tphl at D1 through Path 2 = 0.75ns + 1.0ns + 0.75ns + 0.90ns + 0.18ns = 3.58ns

Falling Signal Analysis (For Path2):
• Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
• Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
• OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of OR gate for ARC b2 -> y2 => (0.5ns, 0.75ns)
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)

For Falling Signal at the Input (Q1), we are getting Rising Signal at the Output (D2) through Path2. So in this scenario, delay between Q1 and D1 through Path2 = Tplh.
Minimum Tplh at D1 through Path 2 = 0.50ns + 0.25ns + 0.50ns + 0.50ns + 0.15ns = 1.90ns
Maximum Tplh at D1 through Path 2 = 1.00ns + 0.75ns + 1.00ns + 0.75ns + 0.20ns = 3.70ns

Solution:
Through Path 1 (Min Tplh) : 2.21ns
Through Path 1 (Min Tphl) : 1.75ns

Through Path 2 (Min Tplh) : 1.90ns
Through Path 2 (Min Tphl) : 1.61ns

Through Path 1 (Max Tplh) : 3.80ns
Through Path 1 (Max Tphl) : 3.36ns

Through Path 2 (Max Tplh) : 3.70ns
Through Path 2 (Max Tphl) : 3.58ns

Overall Minimum Tplh at D2 (when input is at Q1) = 1.90ns (Through Path 2)
Overall Maximum Tplh at D2 (when input is at Q1) = 3.80ns (Through Path 1)
Overall Minimum Tphl at D2 (when input is at Q1) = 1.61ns (Through Path 2)
Overall Maximum Tphl at D2 (when input is at Q1) = 3.58ns (Through Path 2)

In Summary, I can write, At D2 with respect to Q1 Tphl = (1.61ns, 3.58ns) & Tplh = (1.90ns, 3.80ns)

Is it done? I mean do you think Interviewer is going to stop at this point. :) :) Don't ever think. By now they will realize that you are good in below concepts.
• Min and Max Delay Calculation
• Delay calculation based on Timing Arc (I can say some part of Path base & Graph base analysis)
• Tphl and Tplh based Delay Calculation
• Multipath Delay Calculation
• Use of Rising edge and Falling Edge at Input during delay calculation

Now, it's time to check few more concepts related to CELL Delay (Like Cell Delay as a function of Input Transition Vs Output Load) and then how you can use those concepts in delay calculation of Combinational Circuit. :) Lets discuss this in Next Article.

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