## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Monday, October 2, 2017

### Delay Interview Question (Part1)

Let's discuss the Delay concepts from Interview point of view. Several times it happen that Interviewer is going to ask certain questions and the moment you answer it - they will change the case or scenario without changing the Diagram or values. Few of the scenarios, I am going to discussing here. Remember - As a Interviewer - our intension is to check "how much you know" and "How much you can visualize from Tool perspective or real design point of view".

### Example 1:

All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay = (1.25ns, 1.5ns)
OR gate (min, max) delay = (0.3ns, 0.4ns)

Note: These min and max delay numbers are not corresponding to rise and fall delay number.

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
This question is very easy. You have to understand only 1 thing, There are 2 paths and question is all about min and max delay between Q1 and D2.So, you have to calculate both min and max delay with respect to both the paths and then figure out which one is minimum or maximum out of 4 delay values.

Solution:
Path 1 (Min Delay) : 0.25 + 1.25 + 0.1 + 0.3 + 0.1 = 2ns
Path 1 (Max Delay) : 1.0 + 1.5 + 0.2 + 0.4 + 0.2 = 3.3ns

Path 2 (Min Delay) : 0.25 + 0.25 + 0.25 + 0.3 + 0.1 = 1.15 ns
Path 2 (Max Delay) : 1.0 + 1.0 + 1.0 + 0.4 + 0.2 = 3.6 ns

Overall Min Delay between Q1 and D2 = 1.15ns (From Path 2)
Overall Max Delay between Q1 and D2 = 3.6ns (From Path 2)

### Example 2:

All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay = (1.25ns, 1.5ns)
OR gate (min, max) delay = (0.3ns, 0.4ns)

Note: These min and max delay numbers are corresponding to rise and fall delay number respectively.

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
Now this question become tricky. As per Note - I have mentioned that these min and max delays are actually rise and fall delay. If this is the scenario, we have to understand circuit and find out more accurate Min and Max delay between Q1 and D2. Remember, above numbers (Min and Max delay in Example 1) is also correct but we are talking about more accurate number. This is the only trick or say the intension of Interviewer to ask you this question with slightly change in wordings. :)

We have to do 2 type of analysis for each path - Rising & Falling signal analysis at D1 for both paths.

Rising Signal Analysis (For Path1):
• Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
• AND gate is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for AND gate => 1.5ns
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
• OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for OR gate => 0.4ns
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 1 + 1.5 + 0.2 + 0.4 + 0.2 = 3.3ns

Falling Signal Analysis (For Path1):
• Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
• AND gate is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for AND gate => 1.25ns
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
• OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for OR gate => 0.3ns
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 0.25 + 1.25 + 0.1 + 0.3 + 0.1 = 2.0ns

Rising Signal Analysis (For Path2):
• Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
• Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
• Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
• OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for OR gate => 0.4ns
• Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 1 + 0.25 + 1 + 0.4 + 0.2 = 2.85ns

Falling Signal Analysis (For Path2):
• Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
• Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
• Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
• OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for OR gate => 0.3ns
• Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 0.25 + 1.0 + 0.25 + 0.3 + 0.1 = 1.9ns

Solution:
Path 1 (Min Delay) : 2ns (Because of Falling Signal Analysis)
Path 1 (Max Delay) : 3.3ns (Because of Rise Signal Analysis)

Path 2 (Min Delay) : 1.9ns (Because of Falling Signal Analysis)
Path 2 (Max Delay) : 2.85ns (Because of Rise Signal Analysis)

Overall Min Delay between Q1 and D2 = 1.9ns (From Path 2 - Falling Signal Analysis)
Overall Max Delay between Q1 and D2 = 3.3ns (From Path 1 - Rise Signal Analysis)

Do you think that's all .. NO NO NO .. Still there are couple of scenario which can be asked using same figure. Always remember - Interviewer never stop like this. :) :) Check Next Article of this series, where we are discussing about Arc based Delay calculation along with High to Low & Low to high Propagation Delay.

1. This would be a great help since most of the interviewers ask these kind of Questions.

Best Salesforce CRM Courses in Bangalore
Best Oracle DBA Courses in Bangalore
Best Oracle SQL Classas in Bangalore
Best Java classes in Bangalore

2. Nice and good post also

3. Thanks for sharing these questions related to delay which interviewer often ask during interview. It would be the great help for all the interviewees, no doubt.