Translate page

Sunday, October 8, 2017

Physical Design Interview Questions (Part 1)

There are few sets of questions which is very common from Physical Design Interview point of view.
One of my Student shared below questions with me and as I always do - Sharing with everyone. :)

Note: Not mentioning the Answer of these questions right now. But I will do that later on. If anyone of you can do this for me or others (in lesser time compare to my time)- that will be great. I will explain these Answers one by one in detail fashion, so obviously it will take time. :)

First Set of Questions (Asked in One Company)
  1. Draw APR Flow
  2. When we will place "Physical Only Cells"
  3. What are "Spare Cells" and why it is used?
  4. Why do you make clock as Ideal during floorplan & Placement Stage?
  5. What are the different Checks we do in the CTS stage?
  6. What if Setup is failed after manufacturing of chip?
  7. How will you fix Hold?
  8. What is the Importance of useful Skew?
  9. What are DRV Checks and why do we check that?
  10. What is the cross talk? How it will effect the performance?
  11. Cross delay or Cross talk noise is note generally. Why?
  12. A Blocks having 7 Metal layers and same block having 10 metal layer, which will function better and why?
  13. How will you define the shape of the Die?

Other set of questions (Asked in Second Company)
  1. Draw and Explain APR flow.
  2. How will you place Macro?
  3. How will you reduce congestion near I/O parts?
  4. Where will you implement partial blockage?
  5. What are checks you will do after each stage of PNR?
  6. What is Setup and Hold Time?
  7. Few problem based on Setup and Hold Calculation.
  8. What are the Timing check will you do apart from setup and hold check?
  9. What if Setup and Hold Both fails?
  10. How will you resolve Setup and Hold Issues?
  11. What are clock free targets and buffer constraints?
  12. How will you fix DRV?
  13. How will you do cloning?
  14. Which metal will you use for Power routing and Why?
  15. What are routing grids?
  16. What is Antenna Effect and how will you resolve it?
  17. What is Antenna Ratio?
  18. What is Latch up and How will you resolve it?
  19. How will you place TAP Cells and in which Stage will you place Tap cells?
  20. Why ENDCAP Cells are used ?
  21. What all Datas will be given to FAB after Tapout?
  22. Why Derates are used for Timing Calculation? Is it Good or Bad?

I was thinking to list down Companies name here but then realized what if they stop asking these questions. :) :) But Point is these questions are very much related to concepts of whole PD flow. I am not saying that only these questions are sufficient for you to crack any PD (Physical Design) Interview, but I am 100% sure that these will help you to understand if your preparation is good enough and provide you certain direction in your preparation.

In case, you need my help to check whether you are ready for Interview or NOT, Please request for the MOCK Interview. We can connect and you are going to treat as Interviewee. After the MOCK interview, I will provide you detailed feedback.
Steps to request for MOCK Interview Sessions are below.
  1. Fill all details of this Form.
    Registration Form
  2. Book your 30min Slot
  3. After the Mock Interview - Get Detailed Feedback at your Mail id



  1. Thank you sir,
    Realy very helpful for preparation.

  2. This post is very informative and helpful for the people who are trying to get a job in VLSI and are attending interviews.

    Please check the link below-
    Best MSBI Courses in Bangalore
    Best PEGA Training Courses in Bangalore
    Best Oracle PLSQL Training Courses in Bangalore
    Best Advanced JAVA Training Courses in Bangalore

  3. i want answers for these questions , please someone reply


Must Read Article

Related Posts Plugin for WordPress, Blogger...