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Monday, February 28, 2011

Basic of Timing Analysis in Physical Design

STA & SI:: Chapter 1: Introduction
1.1a 1.1b 1.1c 1.2a 1.2b
INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

Lots of people asked me to share my experience over timing analysis. Even though, a lot of material is already present but still it looks to me that things are not in a systematic way. I try my best to put things in a simple and understandable language or say way and wish it helps everyone (beginner and professional).
Please let me know in case I have missed any topic or concept. It’s difficult to put everything in a single post, so be ready for series of articles :) on Timing analysis.

What is Timing Analysis??

Before we start anything, it's important to know "what exactly we mean by Timing Analysis". Why it's so important these days?

There are a couple of reasons for performing timing analysis.
  • Timing Constraints
    • We want to verify whether our circuit meet all its timing requirements
    • There are 3 types of design constraints
      • timing,
      • power,
      • area.
    • During designing there is a trade-offs between speed, area, power, and runtime according to the constraints set by the designer. However, a chip must meet the timing constraints to operate at the intended clock rate, so timing is the most important design constraint.
  • Operating Evniroment:
    • We want to make sure that circuit is properly designed and can work properly for all combinations of components over the entire specified operating environment. "Every Time".
  • Component Selection: Timing analysis can also help with component selection.
    • An example: You are trying to determine the speed of the memory device which can be use with a microprocessor.
      • Using a memory device that is too slow, may not work in the circuit (or would degrade the performance by introducing wait states) and
      • Using one that is too fast will likely cost more than it needs to.

So, I say Timing analysis is the methodical analysis of a digital circuit to determine if the timing constraints imposed by components or interfaces are met. Typically, this means that you are trying to meet all set-up, hold, and pulse-width times requirement.

Note: Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be compromised but not timing!

Types of Timing Analysis:

There are 2 type of Timing Analysis
  • Static Timing Analysis
    • Checks static delay requirements of the circuit without any input or output vectors.
  • Dynamic Timing Analysis.
    • verifies functionality of the design by applying input vectors and checking for correct output vectors

Basic Of Timing Analysis:

The basis of all timing analysis is the "Clock" and "Sequential component" (Flip-flop, Latches). Following are few of the things related to clock and flip-flop which we usually want to take care during Timing analysis.

Clock related:
  • It must be well understood parametrically and glitch-free.
  • Timing analysis must ensure that any clocks that are generated by the logic are clean, are of bounded period and duty cycle, and of a known phase relationship to other clock signals of interest.
  • The clock must, for both high and low phases, meet the minimum pulse width requirements.
  • Certain circuits, such as PLLs, may have other requirements such as maximum jitter. As the clock speeds increase, jitter becomes an increasingly important parameter.
  • When "passing" data from one clock edge to the other, ensure that the worst-case duty cycle is used for the calculation. Remember: A frequent source of error is the analyst assuming that every clock will have a 50% duty cycle.
Flip-Flop related:
  • Make sure that all parameters of flip-flops always met. The only exception is when synchronizers are used to synchronize asynchronous signals
  • For asynchronous presets and clears, there are two basic parameters (Recovery and Removal) must be met.
  • All setup and hold times are met for the earliest/latest arrival times for the clock.
  • Setup times are generally calculated by designers and suitable margins can be demonstrated under test. Hold times, however, are frequently not calculated by designers.
  • When passing data from one clock domain to another, ensure that there is either known phase relationships which will guarantee meeting setup and hold times or that the circuits are properly synchronized

Now, let's talk about Each type of Timing analysis One by one in the series of articles.



  1. Excellent pieces. Keep posting such kind of information on your blog. I really impressed by your blog.

  2. really good site to clear our doubts

  3. Really great job!!! very helpful

  4. I don't know how to address you. Until I know you, will stick to Senior.

    Senior, what we loosing by limiting our selfs to static analysis to fix all the timing issues?

    In real world every thing is dynamic. We do functionality verification with vectors, we simulate ( or emulate if we could afford it. ), which is dynamic !

    But coming to timing we are limiting to static analysis because of resources ( machine time and to reduce the run time of incremental timing analysis by the 'Design automation tools' during synthesis, place n route stages).

    This is costing us something for sure... Am trying to figure it out !


  5. My Mentor told me when ever you come to me with a question, "I also want you bring along all the possible answers, on the basis of your experience and knowledge".

    Senior, in the early days when our fathers decided to stick to timing analysis for only 'Static', we are only needed few more days of work to tune the constraints to reflect dynamic situations of the design application.
    i.e timing exceptions.
    If the timing analysis is dynamic, we don't need to add timing exceptions, in the real dynamic time they don't happen.

    In the current world of system on a single chip, there are too many variable ( a wide variety of IPs ) for engineers to figure out all the timing exceptions that won't occur in the real time.

    I personally witnessed and suffered how not clean constraints munching valuable turn around time for todays complicated SOC design's specs to silicon realization.

    Conclusion : By not doing dynamic timing analysis, we are loosing valuable time and all stages of chip design are suffering. Considering my limited experience and knowledge this might be a false conclusion, please comment.

    The possibility ( or impossiblity ) of implementing a dynamic timing analysis is completely different discussion, and I need to reach out my peers in EDA software development industry to comment on this.


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