## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Monday, December 26, 2016

### UNATE : Timing Arc

 STA & SI:: Chapter 1: Introduction 1.1a 1.1b 1.1c 1.2a 1.2b INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

Previous Article is all about "What is Timing Arc?" and "How can you categorize them (Net Arc and Gate Arc; Delay Arc and Constraint Arc)?"
But still we need to understand how timing arc help us to answer our questions related to any Standard Cell or any Flip-flop or any system (like Macros, IPs)...
1. For a Particular Input (Rising or falling), What type of Output (output is rising or falling or no change) you get ?
2. How much time (may be in the form of Delay) it will take to respond for a particular Input ?
3. Is there any constraint on any pin and if yes, then what are those and on what pin ?

First Question can be Answer if we know: How Input pin is logically connected with Output pin.

What is the meaning of Logically connection? It Means, what is going to happen “For Rising Input"...whether Output
• Fall or
• Rise or
• No Change

Timing Arc help us to identify this with a property known as Unate.

## UNATE

### Unate are of three types:

• Positive Unate:
• Rising Input – Rising Output OR No change in Output.
• If we apply rising signal to the input of a Timing Arc, corresponding output signal is either Rising or there is "No change".
• Falling Input – Falling Output OR No change in Output
• If we apply Faling signal to the input of a Timing Arc, corresponding output signal is either Falling or there is "No change".
• E.g:
• BUFFER
• AND gate (will explain this in detail later below)
• OR gate (will explain this in detail later below)
• Negative Unate:
• Rising Input – Falling Output OR No change in Output.
• If we apply rising signal to the input of a Timing Arc, corresponding output signal is either Falling or there is "No change".
• Falling Input – Rising Output OR No change in Output
• If we apply Falling signal to the input of a Timing Arc, corresponding output signal is either Rising or there is "No change".
• E.g:
• Inverter (NOT gate)
• NAND gate (will explain this in detail later below)
• NOR gate (will explain this in detail later below)
• Non_Unate:
• The non-unate represents a function where change in output value cannot be determined from the direction of the change in the input value. Output pin value is not dependent on single Input Pin. It also depends on 2nd Input pin. Since Timing arc will be between the Single Input and Single Output pin, so it’s difficult to identify this relationship directly.
• E.g:
• XOR gate (will explain this in detail later below)
• XNOR gate (will explain this in detail later below)

### Buffer:

In the Buffer there is one input pin and one output pin. Behavior of Buffer we all know.
• Rising Input results Rising Output.
• Falling Input results Falling Output.

So, Timing Arc between Input and Output pin of Buffer are Positive Unate.

Remember, there are 2 Timing arcs in Buffer: One for Rising Edge and other for Falling edge.

### Inverter:

In the NOT Gate (Inverter) there is one input pin and one output pin. Behavior of Inverter also we know very well.
• Rising Input results Falling Output.
• Falling Input results Rising Output.

So, Timing Arc between Input and Output pin of Inverter are Negative Unate.

Remember, there are 2 Timing arcs in Inverter: One for Rising Edge and other for Falling edge.

### AND Gate:

Above is the "Truth Table" of AND gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - No change (constant at 0)
A = 1 , B (0-> 1) ; Y - Changes from 0-> 1

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - No change (constant at 0)
B = 1 , A (0-> 1) ; Y - Changes from 0-> 1

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - No change (constant at 0)
A = 1 , B (1-> 0) ; Y - Change from 1-> 0
B = 0 , A (1-> 0) ; Y - No change (constant at 0)
B = 1 , A (1-> 0) ; Y - Change from 1-> 0

So, in both the cases - Timing arc between A-Y and B-Y is Positive Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in AND gate:
1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

### OR Gate:

Above is the "Truth Table" of OR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 0-> 1
A = 1 , B (0-> 1) ; Y - No change (constant at 1)

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 0-> 1
B = 1 , A (0-> 1) ; Y - No change (constant at 1)

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 1-> 0
A = 1 , B (1-> 0) ; Y - No change (constant at 1)
B = 0 , A (1-> 0) ; Y - Change from 1-> 0
B = 1 , A (1-> 0) ; Y - No change (constant at 1)

So, in both the cases - Timing arc between A-Y and B-Y is Positive Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in OR gate:
1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

### NAND Gate:

Above is the "Truth Table" of NAND gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - No change (constant at 1)
A = 1 , B (0-> 1) ; Y - Changes from 1-> 0

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - No change (constant at 1)
B = 1 , A (0-> 1) ; Y - Changes from 1-> 0

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - No change (constant at 1)
A = 1 , B (1-> 0) ; Y - Change from 0-> 1
B = 0 , A (1-> 0) ; Y - No change (constant at 1)
B = 1 , A (1-> 0) ; Y - Change from 0-> 1

So, in both the cases - Timing arc between A-Y and B-Y is Negative Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in NAND gate:
1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

### NOR Gate:

Above is the "Truth Table" of NOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 1-> 0
A = 1 , B (0-> 1) ; Y - No change (constant at 0)

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 1-> 0
B = 1 , A (0-> 1) ; Y - No change (constant at 0)

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 0-> 1
A = 1 , B (1-> 0) ; Y - No change (constant at 0)
B = 0 , A (1-> 0) ; Y - Change from 0-> 1
B = 1 , A (1-> 0) ; Y - No change (constant at 0)

So, in both the cases - Timing arc between A-Y and B-Y is Negative Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in NOR gate:
1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

### XOR Gate:

Above is the "Truth Table" of XOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 0-> 1
A = 1 , B (0-> 1) ; Y - Changes from 1-> 0

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 0-> 1
B = 1 , A (0-> 1) ; Y - Changes from 1-> 0

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 1-> 0
A = 1 , B (1-> 0) ; Y - Change from 0-> 1
B = 0 , A (1-> 0) ; Y - Change from 1-> 0
B = 1 , A (1-> 0) ; Y - Change from 0-> 1

This one is little bit different from other gates (which we have reviewed till now).
You can see that change in the output can't be decided just by seeing/observing one input pin. For B changes from '0' to '1', output can change from '1' to '0' or '0' to '1' depends on the value at A. In other way, I can say that change in the output don't have any pre-defined pattern with respect to Pin B or Pin A indivisibly. It depends on collective behavior of A and B.
Such type of Timing Arcs neither fall in the category of positive_unate nor in negative_unate. These Timing Arcs are Non_Unate.

Timing arc between A-Y and B-Y is Non Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in XOR gate:
1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

### XNOR Gate:

Above is the "Truth Table" of XNOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 1-> 0
A = 1 , B (0-> 1) ; Y - Changes from 0-> 1

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 1-> 0
B = 1 , A (0-> 1) ; Y - Changes from 0-> 1

In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 0-> 1
A = 1 , B (1-> 0) ; Y - Change from 1-> 0
B = 0 , A (1-> 0) ; Y - Change from 0-> 1
B = 1 , A (1-> 0) ; Y - Change from 1-> 0

Explanation is same as in case of XOR gate. (copy paste the same paragraph here :) )
You can see that change in the output can't be decided just by seeing/observing one input pin. For B changes from '0' to '1', output can change from '1' to '0' or '0' to '1' depends on the value at A. In other way, I can say that change in the output don't have any pre-defined pattern with respect to Pin B or Pin A indivisibly. It depends on collective behavior of A and B.
Such type of Timing Arcs neither fall in the category of positive_unate nor in negative_unate. These Timing Arcs are Non_Unate.

Timing arc between A-Y and B-Y is Non Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in XNOR gate:
1. Input Pin A to Output Pin Y for Rising Edge
2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

I am sure, by now, you have developed or revise the concept of Unate in Timing Arc. With the help of Truth table, you can easily figure out the Unateness of any Timing arc. Even If you are going to design any circuit or system (which is not in the list of Standard gates), then you can yourself figure out the Unateness property of different Timing arcs in that system.

We will discuss about that in more detail in next few article. Like how these (Timing Arc , Unateness ) represent in Timing Library, how different values are captured in Timing Library and a lot about the Timing Arcs. :)

### Interview Questions

I have tried to capture few Interview questions here which can help you big time during your preparation.
1. What are the different types of Timing Arc ?
2. What is Unateness of a Timing Arc ?
3. What do you mean by Positive_unate of a Timing Arc?
4. What do you mean by Negative_unate of a Timing Arc?
5. What is the difference between Non-unate Timing arc and Positive Timing Arc ?
6. How many Timing Arcs are present in case of Buffer?
7. How many Timing Arcs are present in a 2 input NAND gate?
8. How to represent Timing Arcs in the Timing Library ?
9. A timing arc is positive Unate, if we apply rising edge at the input of the Timing arc, corresponding output will change or not ?
10. How many Timing arc is present for a 3 input XOR gate?
11. What's the Unateness of different Timing Arc for a 3 input XNOR gate ?

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9. 10. can you give a brief about the unateness of three input xor gate ?

11. 12. Sir, dont mind,

timing arcs types : a) net arc and b) cell arc

then,unate in timing arc, means do we need to consider only net arcs?

i have doubt, that difference between these two questions:
1) how many timing arc in a Buffer?
ans: 2 net arc and 1 cell arc and 2 arc wrt unate. total = arcs!

2) how many timing arc in buffer wrt unate?
ans: 2 arcs (rising edge and falling edge)

kindly solve this doubt.

13. Hi,is there any be arc between d and q.