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Thursday, September 24, 2015

Design Exchange Format (DEF)

Introduction to Design Exchange Format (DEF)

Design Exchange Format (DEF) . is used to represent the physical layout of an IC in an ASCII format. It represents the netlist and circuit layout. We used DEF along with LEF (Library Exchange Format) to represent complete physical layout of an integrated circuit while it is being designed.

Origin : DEF was developed by Cadence Design Systems.

Generated by : Usually generated by place and route (P&R) tools and are used as an input for post analysis tools, such as extraction tools or power analysis tools.

Now here I am not going to describe the different syntax used in the DEF, But I will concentrate on what exactly DEF is!
Actually DEF is a text file which you can read and easily figure out the different information about the layout. like
  • What are different components in your design ?
  • Where these components are placed in you DIE ?
  • How these components are places ?
  • What's the size of the DIE ?
In Semiconductor terminology, it will tell you the
  • Macros of design
  • Placement information
  • Pin locations
  • Metal blockages
  • Orientation
Now let me explain this with the help of 1 example of you house. You have to draw a picture as per my description mentioned below.
  • You have a plot of 100x100 meter
  • You have to keep a margin of 2m at all the four side. Margin - Open area, no construction should be done in that area.
  • From coordinates (2,2) to (10,10) - it's a 8x8 meter Kitchen area
  • There are 2 doors of 7ft in height from 10,5 to 10,6 and 2,10 to 3,10.
  • One T shape Hall (along with a small pathway) is present which has following coordinates. (10,2) (10,10) (2,10) (2,14) (10,14) (10,40) (40,40) (40,2)
  • One master Room is present with coordinates (2,14) (10,60)
  • One attached balcony with the Master Room with coordinates (2,60) (10,80).
  • From (10,40) (50,80) another Room
  • Attached bathroom (50,40) (60,80)
  • (40,40)(60,20) is used for Stairs
  • These Stairs will go till 3rd Floor, so no other construction on top of this place
  • (40,20) (60,2) - third room
Now If I will provide you this much of info, you can easily come up with a Layout. 
Similarly, we can define the Door location / Window Location, Electricity fitting, Pipe line and all. Lets try to correlate the same with the VLSI terminology and then you can easily figure out what all are present in the DEF.

Plot size >> Core Size / Die Size
Rooms and Kitchen >> Macro placement
Kitchen / Bedroom / Bathroom >> Different Blocks with some characteristic. Which we also define in DEF.
Window/Door Location >> Pin placement
Passage >> Routing Information
Floors >> Metal layer Stack
Open Space info >> Related to Blockage information.
Entrance to House >> Pin location which Interact with outside world.

There are few more info which you can define as Part of DEF.
  • Specifies that the component has a location and cannot be moved by automatic tools, but can be moved using interactive commands.
  • For specifying the Hierarchy name, which Divider Character you want to use "." or "/" can be defined in DEF.
  • Metal Fill Details
  • Units for different type of Dimension related info
  • Defines any Non Default Rules (NDR) used in this design that are not specified in the LEF file.
  • Pin related info. Like
    • Which type of Pin it is ?
    • Pin connection (in case it's connected to Ground or Power VSS/VDD)
    • It's a power pin or Signal Pin or Clock Pin or SET/Reset pin etc
    • Pin orientation
  • Rows, Sites, Tracks
    • Placement of Standard Cells are done by the tool (Automated Process).
    • Think the difference when I will ask you to arrange 100 things in a Big Box Vs In a Almeria which have drawers. In Box - you can put all the stuff but that will not be so organized as it will be in Drawers.
    • In the drawers, you have to follow certain rules (size of Drawers and spacing between Drawers).
    • There may be more space available in Box but it's difficult to reach those Items very easily randomly
    • Similarly, in Design we come up the concept of Rows, Sites, Tracks.
    • During the placement it's easy for Tool to place different standard cells or macros with in these Rows / Sites.
    • Tracks helps during Routing.
    • You can correlate these with the Foundation and Pillars during Home construction which provide a frame for placing the Bricks between them.

You will get the layout information above Metal1 in the DEF. It will not contain any info about the Diffusion or Poly or any other layer which are below Metal1. And that the reason it's Used in Digital Design. Means when we are talking about LEF/DEF flow - means we are talking about Digital Flow.

Now there are few things which you will not define as part of House layout because that info you will get somewhere else. Sink / Taps / Electric fittings, Size and shape are predefined. So you don't have much control. You can choose which one you want to use but you will not prefer to manufacture those one. You can consider these are like Standard Cells, which are already defined and designed by someone else. You have to just place those things. Whatever minimum information you require during you Designing the layout, that info you can get through Standard Cell LEF. We will discuss about LEF in Next Article.

I think, I have tried to cover each and every thing which should be part of DEF. Now just Syntax is remaining. Few of them are:

[ VERSION statement ]
[ DIVIDERCHAR statement ]
[ BUSBITCHARS statement ]
DESIGN statement
[ TECHNOLOGY statement ]
[ UNITS statement ]
[ HISTORY statement ] ...
[ DIEAREA statement ]
[ ROWS statement ] ...
[ TRACKS statement ] ...
[ GCELLGRID statement ] ...
[ VIAS statement ]
[ STYLES statement ]
[ REGIONS statement ]
[ COMPONENTS section ]
[ PINS section ]
[ BLOCKAGES section ]
[ SLOTS section ]
[ FILLS section ]
[ SPECIALNETS section ]
[ NETS section ]
[ SCANCHAINS section ]
[ GROUPS section ]
[ BEGINEXT section ] ...
END DESIGN statement

You can get more detail about the Syntax and their Description from the Below Document:

Wednesday, September 23, 2015

Blockage: Placement and Routing In design

Blockage In Design

There are 2 type of Blockage from definition point of view.
  1. Placement
  2. Routing

Blockage can be Area specific or can be Component Specific (associated with Instance). If it's associated with any Instance - Means - the moment you move Instance from one location to other (with in the Chip), Blockage also move along with that.

You can also associate the type of components which you want to block. like
  • Standard Cell
    • If you are saying that you have applied Standard Cell Blockage in a area, Means you don't want tool place Standard Cell in that certain area. And that's the reason such Blockage we termed as "Standard Cell Blockage"
    • Question is: What is the need of this?
      • There are some areas which we want to reserve for Routing purpose and that's the reason we don't want to put standard cells there. Usually we do this to reduce the congestion in a particular area.
      • Some time we are okay with the inverter and buffer in certain area but don't want to put any other Standard Cell Blockage. Like between 2 Adjacent Macros. In this area there is a narrow channel and if we will put standard cell then it can create a Congestion, so avoid placing standard Cell. But in that area there are pins of macros and there may be requirement that you need to put buffers or inverter before those pins (to increase the drive strength or improve transition time or invert the logic). So you have to allow these 2 type of Standard Cells. These are termed as "Non-Buffer Blockage".
  • Macros (Halo) blockage : usually placed around Macros so that no other macro sit adjacent to that (To save routing congestion at later stage)

In case of Routing Blockage, you have to define Layer Number which you want to block. I means to say, there is a area X and In that area you don't want any net to be routed using the Layer M1,M2,M3 but you are okay with M4 passes over that area. Such type of Blockage comes into the category of Routing Blockage.

Similarly, you can also Block a reason for a particular type of Net (on basis of Net property). Like you want to block a Signal Net but there is no issue with the Power Net. In that case, any signal nets on any layer will not cross that area but Power Net can be easily routed in that area.

You can ask what's the reason of doing this. Why we don't want to route a particular type of Net or Particular Metal layer over a certain region.

Simple Ans is:
Suppose you have a Block/Macro which is noise sensitive and you want to prevent any signal routing on specific layers above the block Because signal has a nature to change or fluctuate, which can introduce Noise in that block. Based on the Sensitivity factor toward the Noise and Noise margin you can decide whether you have to block all the layers of some specific layers.

Suppose topmost routed layer inside Block/Macro is M2 and block is sensitive up to 2 level of Metal layers (M3 and M4), then you can block only these 2 metal layers and allow other metal layer routed on the top of such Macros/Blocks.

But in case it's very-very sensitive with any change in the signal in any layer and also Noise margin is very less, then you can block all the Signal Nets (on any layer). But in that case you are okay if Power rail passes over that (I am sure you know the reason :)). Power Signal may be either VSS or VDD - means "0" or "1" and don't change frequently. Even if they are changing at any point of time (when you are doing shutdown, disconnect a particular block) there should not be any issue because such things happen in the time frame which is far-far bigger then the clock frequency. E.g. After 1 hr for a Block which is working on 10GHz frequency. Means you have to block only signal Nets.

By Now, I think you are clear with the concept of Routing Blockage.

You can place the Blockage for Metal Fills. Means no Metal fill can be placed in that area. why this requirement ? Do some brainstorming.. :) :) Just few hints on which you can think.
  1. Why we do Metal fill ?
  2. How it will effect the CAP or say timing of circuit ?
  3. At which step you are doing Metal Fills?

EDA Tool also give you the Flexibility to define the percentage of Blockage. Like, In a particular area, density of standard cells should not be greater then 50%. What exactly we are doing here - We are telling tool that they can place the standard cells in this area till the time it's occupancy is less then 50%. Once that's achieve, no more standard cell is required. There are few reasons of this.
  • We are doing this early in the design, to save this place of Routing resources later on.
  • We don't want congestion. (other way to say above point)
  • We want to use this place for future optimization.
  • We want to use this place for Clock tree buffer insertion.

Other type of Blockage on the specified layer where slots cannot be placed.

In the last I want to stress on 2 points (which if you remember, will help you a lot)
  1. Blockage is a feature which Tool provides to user. Any type of Blockage can be possible if Tool allow. In case tool don't allow then you have to figure out any other way. If EDA vendor come to know that it's a good feature and help other customer also, they can implement it in their tool with a new Switch :).
  2. You can apply any Blockage at any point of time (before any particular Step of Physical Design PD) and can remove any point of time. It will help you a lot from Design perspective + methodology side

Example of #1 - I have explained later in the article.
Example of #2 - Suppose you don't want to place any Clock Net in a particular reason but okay with other Type of nets. Best thing to do it - Apply Routing Blockage during the CTS (At the time you are creating the Clock net structure) and no need of any such blockage before and after this.
Note: Scenario #2 is very common in the Industry.

Interview Questions:

Now let me capture few Questions on this Topic, which can be asked in a Interview or May be it will help you to understand this Topic more clearly. Do the Discussion with your friends and Read this article again and again if you don't figure out the Answer. :)
  1. What do you mean by Routing Blockage ?
  2. My design has 7 metal layer stack. Can I block a specific layer (not to route) on a specific area ?
  3. What about if I want to Block only M3 and M5 ? Can I do that ? What's the disadvantage of this ?
  4. Why someone want to block only "Signal Nets" and allow "Power Nets" ?
  5. In which Scenario, we also prefer To Block Power Nets (Power Ground Nets) ?
  6. When we are Applying Routing Blockage over a certain area, is it only for Global routing / Detailed Routing or for Both ?
  7. Suppose, 2 macros are communicating with each other and I don't want them to Interact using the routing resource of M3. Can I do that ? If Yes how ?
  8. Can I block VIAs also ?
  9. If I want to block only specific Nets like Critical Nets or say "Clock Network Nets" in a particular area. Can we do that ?
  10. What do you mean by the "Placement Blockage"?
  11. Can we place the blockage for Metal Fill only? If yes, Why we want to do this ? Can't this be controlled using Metal Density rules ?
  12. There are 2 type of Metal Fills (Floating and Grounded). Is it possible that I create a blockage only for Those metal fills which are grounded ?
  13. There are some special Cells, like ENDCAP CELLS , TAB CELLS, Level shifter. I want to create a blockage only for these specific Cells. Can I do that and if Yes How ?
  14. Can I create a Blockage which is specific to Scan-Chain related FF. Means no FF in a particular area which are part of Scan chain logic.
  15. Why we want to use the Macro Blockage ? What's the need of that ? In which area/scenerio we recommend to use Macro Blockage ?
  16. What do you mean by Soft and Hard Blockage ?
  17. What's the Partial Blockage? What's the advantage of this type of Blockage ?

I can think only these questions right now which can be asked or usually asked from a candidate. They can ask the definition or the reason behind that (Logic).

Above I have a "Question related to 2 macros communicating and you don't want any net on Layer Metal3." This is the perfect example where No tool provide such feature because there is no direct command to do this. But you can write a script which can do this. Like capture those pins which are communicating with each other. During Routing define the constraint that M3 will not be used for any Net which has these input-output pin combination at there extreme end. So what you have done, with the help of a script you can achieve this.

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