Translate page

Wednesday, September 23, 2015

Blockage: Placement and Routing In design

Blockage In Design

There are 2 type of Blockage from definition point of view.
  1. Placement
  2. Routing

Blockage can be Area specific or can be Component Specific (associated with Instance). If it's associated with any Instance - Means - the moment you move Instance from one location to other (with in the Chip), Blockage also move along with that.

You can also associate the type of components which you want to block. like
  • Standard Cell
    • If you are saying that you have applied Standard Cell Blockage in a area, Means you don't want tool place Standard Cell in that certain area. And that's the reason such Blockage we termed as "Standard Cell Blockage"
    • Question is: What is the need of this?
      • There are some areas which we want to reserve for Routing purpose and that's the reason we don't want to put standard cells there. Usually we do this to reduce the congestion in a particular area.
      • Some time we are okay with the inverter and buffer in certain area but don't want to put any other Standard Cell Blockage. Like between 2 Adjacent Macros. In this area there is a narrow channel and if we will put standard cell then it can create a Congestion, so avoid placing standard Cell. But in that area there are pins of macros and there may be requirement that you need to put buffers or inverter before those pins (to increase the drive strength or improve transition time or invert the logic). So you have to allow these 2 type of Standard Cells. These are termed as "Non-Buffer Blockage".
  • Macros (Halo) blockage : usually placed around Macros so that no other macro sit adjacent to that (To save routing congestion at later stage)

In case of Routing Blockage, you have to define Layer Number which you want to block. I means to say, there is a area X and In that area you don't want any net to be routed using the Layer M1,M2,M3 but you are okay with M4 passes over that area. Such type of Blockage comes into the category of Routing Blockage.

Similarly, you can also Block a reason for a particular type of Net (on basis of Net property). Like you want to block a Signal Net but there is no issue with the Power Net. In that case, any signal nets on any layer will not cross that area but Power Net can be easily routed in that area.

You can ask what's the reason of doing this. Why we don't want to route a particular type of Net or Particular Metal layer over a certain region.

Simple Ans is:
Suppose you have a Block/Macro which is noise sensitive and you want to prevent any signal routing on specific layers above the block Because signal has a nature to change or fluctuate, which can introduce Noise in that block. Based on the Sensitivity factor toward the Noise and Noise margin you can decide whether you have to block all the layers of some specific layers.

Suppose topmost routed layer inside Block/Macro is M2 and block is sensitive up to 2 level of Metal layers (M3 and M4), then you can block only these 2 metal layers and allow other metal layer routed on the top of such Macros/Blocks.

But in case it's very-very sensitive with any change in the signal in any layer and also Noise margin is very less, then you can block all the Signal Nets (on any layer). But in that case you are okay if Power rail passes over that (I am sure you know the reason :)). Power Signal may be either VSS or VDD - means "0" or "1" and don't change frequently. Even if they are changing at any point of time (when you are doing shutdown, disconnect a particular block) there should not be any issue because such things happen in the time frame which is far-far bigger then the clock frequency. E.g. After 1 hr for a Block which is working on 10GHz frequency. Means you have to block only signal Nets.

By Now, I think you are clear with the concept of Routing Blockage.

You can place the Blockage for Metal Fills. Means no Metal fill can be placed in that area. why this requirement ? Do some brainstorming.. :) :) Just few hints on which you can think.
  1. Why we do Metal fill ?
  2. How it will effect the CAP or say timing of circuit ?
  3. At which step you are doing Metal Fills?

EDA Tool also give you the Flexibility to define the percentage of Blockage. Like, In a particular area, density of standard cells should not be greater then 50%. What exactly we are doing here - We are telling tool that they can place the standard cells in this area till the time it's occupancy is less then 50%. Once that's achieve, no more standard cell is required. There are few reasons of this.
  • We are doing this early in the design, to save this place of Routing resources later on.
  • We don't want congestion. (other way to say above point)
  • We want to use this place for future optimization.
  • We want to use this place for Clock tree buffer insertion.

Other type of Blockage on the specified layer where slots cannot be placed.

In the last I want to stress on 2 points (which if you remember, will help you a lot)
  1. Blockage is a feature which Tool provides to user. Any type of Blockage can be possible if Tool allow. In case tool don't allow then you have to figure out any other way. If EDA vendor come to know that it's a good feature and help other customer also, they can implement it in their tool with a new Switch :).
  2. You can apply any Blockage at any point of time (before any particular Step of Physical Design PD) and can remove any point of time. It will help you a lot from Design perspective + methodology side

Example of #1 - I have explained later in the article.
Example of #2 - Suppose you don't want to place any Clock Net in a particular reason but okay with other Type of nets. Best thing to do it - Apply Routing Blockage during the CTS (At the time you are creating the Clock net structure) and no need of any such blockage before and after this.
Note: Scenario #2 is very common in the Industry.

Interview Questions:

Now let me capture few Questions on this Topic, which can be asked in a Interview or May be it will help you to understand this Topic more clearly. Do the Discussion with your friends and Read this article again and again if you don't figure out the Answer. :)
  1. What do you mean by Routing Blockage ?
  2. My design has 7 metal layer stack. Can I block a specific layer (not to route) on a specific area ?
  3. What about if I want to Block only M3 and M5 ? Can I do that ? What's the disadvantage of this ?
  4. Why someone want to block only "Signal Nets" and allow "Power Nets" ?
  5. In which Scenario, we also prefer To Block Power Nets (Power Ground Nets) ?
  6. When we are Applying Routing Blockage over a certain area, is it only for Global routing / Detailed Routing or for Both ?
  7. Suppose, 2 macros are communicating with each other and I don't want them to Interact using the routing resource of M3. Can I do that ? If Yes how ?
  8. Can I block VIAs also ?
  9. If I want to block only specific Nets like Critical Nets or say "Clock Network Nets" in a particular area. Can we do that ?
  10. What do you mean by the "Placement Blockage"?
  11. Can we place the blockage for Metal Fill only? If yes, Why we want to do this ? Can't this be controlled using Metal Density rules ?
  12. There are 2 type of Metal Fills (Floating and Grounded). Is it possible that I create a blockage only for Those metal fills which are grounded ?
  13. There are some special Cells, like ENDCAP CELLS , TAB CELLS, Level shifter. I want to create a blockage only for these specific Cells. Can I do that and if Yes How ?
  14. Can I create a Blockage which is specific to Scan-Chain related FF. Means no FF in a particular area which are part of Scan chain logic.
  15. Why we want to use the Macro Blockage ? What's the need of that ? In which area/scenerio we recommend to use Macro Blockage ?
  16. What do you mean by Soft and Hard Blockage ?
  17. What's the Partial Blockage? What's the advantage of this type of Blockage ?

I can think only these questions right now which can be asked or usually asked from a candidate. They can ask the definition or the reason behind that (Logic).

Above I have a "Question related to 2 macros communicating and you don't want any net on Layer Metal3." This is the perfect example where No tool provide such feature because there is no direct command to do this. But you can write a script which can do this. Like capture those pins which are communicating with each other. During Routing define the constraint that M3 will not be used for any Net which has these input-output pin combination at there extreme end. So what you have done, with the help of a script you can achieve this.


  1. How can I decide the partial placement blockage percentage? What factors need to be taken into account and is there any mathematical equation to come up with this ?

    1. Hi Karthik,
      Partial placement blockage is a concept. It will help you lot during the PD. Consider a scenario - you want to reserve some space in your design for manual routing later in the design in a particular area because as per your experience (in previous design) you have figured out that there are more requirement of this.
      What's the best way to do this?
      You can't block all that area to place the standard cell - you can't block that area completely for routing.

      Then this Technique helps you.

      Just say that 75% using of this area (of say just 25% is sufficient for you in later stage) is okay for you. SO use this option (this type of blocking) which will force tool not to completely utilize this area. Once this is done - you can use it later on.

      Another scenario - there is routing congestion in some area and utilization is 100% but there are some areas in the design where utilization is less then 50%. Since you are using tools for everything and you don't want to do manually (shifting and all), you can use this concept.
      The place where utilization is 100% - place less standard cell. When I am saying "less" - it sound good but how tool will come to know what is less and what is more. This option (partial blocking) is the way to tell your tool. You can say put only 50% of maximum amount of standard cell (Means 50% of available resources in that area). Now if in that area (where congestion was present initially), you place less standard cell - chances of congestion reduce. These extra cells can be placed somewhere else (most probably the same place where utilization is less).
      So in this way - You can think of several uses of this option.

    2. Thank You birdyGURU for the inputs.
      We've used it and are using extensively in our designs. But arriving at the right size of the blockage sometimes needs a lot of iterations. Except for cases where previous experiences help (if we are doing the same design targeted for a lower node). So, I had a question, if we can come up or do have any math equation that suggests the blockage to be used after an initial iteration of floorplan and placement.

    3. If we get congestion because of partial blockage at some area then what we have to do

  2. Hi i could find trim blockgae in tool. What type of blockage is it?? Can u please brief me about the same..Thanks

  3. what is HVT,LVT,SVT ? and i want schematic diagram of those !

    1. HVT is high threshold voltage, LVT is low threshold voltage, SVT is standard threshold voltage. These are different variants of transistors. There is not separate schematic for those

  4. why we apply halo around macros?

    1. The halo/obstruction is the placement blockage defined for the standard cells across the
      boundary of macros so that there is no detouring of the routes if two macros are kept close to each other and are interacting with each other directly

  5. halo are applied around the macros in order to stop the tool to place std cells near the macros so that if there are two macros interacting with each other there is no std cell present in between them which cause the routes to detour causing more delays in the path.

  6. I want the answer of 13 and 14 question . and how we can do that


Must Read Article

Related Posts Plugin for WordPress, Blogger...