## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

# Introduction

In the combinational circuits, output at any given point of time depend only on the input at that time and no relationship with the past inputs. Same thing I can say in different way.
• Circuit respond to the input without any delay (so that even if you apply any other input, it will not effect the output correspond to previous input)
• The time interval between the two successive inputs are so long that within that time circuit respond to the first input.(Means when you apply second input, output is already generated correspond to first input).

but there are situations when an output depends on the present input and condition of the circuit at that time ,which is because of previous input/inputs. This (condition of circuit because of previous inputs) is consider as "storing" the information (means there is a "Memory element") correspond to past inputs.

Note : Basic difference between the Sequential circuits and Combinational Circuits are already explained in the Topic "Combinational Circuits".

Now from definition point of view we can say that
" A digital Circuit is a sequential circuit if it's outputs at any given time are function the external inputs at that time and sequence of past inputs. "

On the basis of tis definition we can classify sequential logic into two models.
• Mealy Model
• Moore Model

From the above figure, you can see that there are 2 types of Inputs
• Primary Inputs from External World
• Secondary Inputs which describe the condition of circuit at the arrival of present inputs.

On the basis of Output from the Combinational Circuit, these two models (Mealy and Moore) are classified.

In Mealy Model - External Outputs depend both on inputs from outside world and on the feedback inputs from memory.

In Moore Model - Output does not depend directly on external inputs. External Inputs causes changes in memory, after which external output emitted from the memory.

In both the above model two thing are hidden which may be or may not be figured out by you.
1. Expected output correspond to every Input
2. "Stability of circuit".
Expected Output correspond to every Input
When ever you apply a input to a circuit, you always expect certain output. Even in above models (Mealy and Moore), when ever you apply a input you know the state of the circuit (condition of the circuit because of the pervious inputs), so it's easy for you to predict the output after certain time (because you have designed that circuit). In case, we don't get expected output, we start tracking back the reason of that.

Stability Of Circuit:
You have applied 1 input which will make some changes in the state of the combinational unit, which is then make changes in the Memory unit (so called feedback unit). Output of the memory unit, which is again feed back as input to the combinational circuit changes the state of the combinational circuit. This process goes on till the time circuit become stable.

From the time of the initial change in input and the final change in output takes place there is a period of instability. If a further change in primary input takes place during this period of instability. the circuit might fail to give a expected output because it isn't clear what the contents of memory are when second input applies. There are changes of the Glitch.

Note:
Lets assume that you provide a input to a circuit and you are expecting some output, but before output settles to your expected value, there is/are some unwanted transitions (one or more). And these Transitions are known as Glitches.

There is only one good solution of this problem. Disconnect the whole system (circuit) from the external world till the time it become stable. Once It become stable, reconnect it. This Disconnect and reconnect usually done with the help of an extra signal, commonly known as Clock (some time Terminology "Enable Signal" also works).

Note:

Now we can say that there are 2 Types of Sequential Circuit
1. Non-Clocked Sequential Circuit
2. Clocked Sequential Circuit

In a Design there may be several clocked sequential circuits interconnected which have different Enable signal (Connect and Reconnect Signal from the External World - Clock Signal). Means One circuit is clocked by CLK1 and other is CLK2 are interconnected. If that's the case, again same problem came into the picture as we have discussed above. Because one circuit don't know when other circuit become stable (or say produce a output after internal stability). So they can't be disconnect or connect as per the other circuit's output (Both circuits are not synchronize with each other). Again same case of Glitch can be there.
If both circuit can be synchronize with each other, this problem solved. And this can be done with a common Clock signal. :) So I can say from Definition point of view that
"If all the enabling clocks in Interconnected circuits are the same, then activity in all circuits will occur synchronously. Such Circuits are known as Synchronous Sequential Circuits".

That Means above category can be renamed as (which is more common)
1. Synchronous Sequential Circuits ( Clocked Sequential Circuit)
2. Asynchronous Sequential Circuits ( Non-Clocked Sequential Circuit)
Note: Difference about these 2 type of circuit already discussed in the Article "Combinational Circuits"

In the next Article, we will discuss more about the Synchronous Sequential Circuits.

# Introduction: "Why Low Power is in Demand in Semiconductor Field"

This series consists of several Article related to Low power concepts. You might be thinking that why this series because already a lot of material is present over the Net about this. And my simple Answer of this – I want to discuss all these details once again on the basis of my experience. I will try to present it in simpler language / Style which can help you to understand the concepts. I came across several articles which require some basic understanding at least. But here I will try to capture the things in such a way that anyone can understand low power concepts.
I can only try – let’s see how much I can get success. 

Very first question is why “Power is such a Big concern and need a solution”? Why everyone is talking about power and especially Low power.
Before I will explain this in more technical way, let me try it in layman language. All of us use cell phone and as the complexity/feature of the phone increases, battery backup decreases. In the market everyone is trying to get more battery backup without compromising with the Features of Cell phone. How it can be possible? Only one way is to reduce the battery consumption (power consumption) of the cell phone. Or I can say that cell phone should start functioning (in the similar fashion as before) in less power (low power consumption). That’s the reason everyone is talking about low power.
In the Semiconductor Industry, It’s a big concern. On the top of this the size of chip decrease day by day and so Power consumption is getting more and more importance. You may be thinking that if you decrease the size of the device, power consumption should also decrease. But unfortunately Power consumption is not directly proportional to size of the chip. (I will explain this in more detail later).

For higher technology nodes (may be higher than 320um), main parameters of concern were:
• Timing
• Area.

In the lower nodes, even after reducing supply voltages, threshold voltages (which reduce the power consumption drastically) power consumption is not in the same proportion as we were expecting. This is all because of several factors. One best example is Leakage current. The device (transistor) densities and clock frequencies also increases for lower nodes which increases power consumption. So in short there are several ways which helps to reduce the power consumption but on other side there are several factors which increase the power consumptions.
In this series, we will discuss all these things in detail.
Right now it’s very important for you to understand that power consumption levels have reached their acceptable limits (now a days) and that’s the reason power has become as important as timing or area.
So now we have 3 main parameters of concern:
• Timing
• Area
• Power

(Note: In this series, we will discuss only about 3rd component - Power :).

Below are few points which will further help you to understand why now a day’s power consumption increases and why it’s important to discuss low power solutions. (These are just few points but in actual there are lots).
• Shrinking feature Size (You might be thinking that for smaller gate the power consumption should be less then how this can be cause of high power.)
• Gate densities have grown faster than scaling theory predicts.
• Number of metal layers increased too
• Wiring and gates are not scaled equally
• Gates are not scaled equally in all dimensions
• So overall consumption of Power increases.
• Leakage power increases as feature sixe decreases.
• Faster processing speeds
• More switch On – Switch Off
• More charging and discharging.
• More power consumption.
• More functionality
• More power requirement.
• Implementation of analog functions in digital
• high speed, high complexity DSP
• continuous data
• High Die temperature
• If power dissipation is not proper, temperature of gate/device increase
• Lots of characteristic (like ON current) are temperature dependent. So hotter the area, more chances of fail of a chip in that area (if not taken care while designing).
• For chip to work, output drivers need to be over-specified/characterized to guarantee drive at maximum ambient temp
• This means increased power dissipation at all temps
• High Power consumption increases (because of any of the above reason)
• The temperature of the chip.
• Sufficient heat sinks and cooling system is required which are expensive and some time bigger than the devices.
• Reduces the battery Life. So require the bigger battery or powerful batteries which are expensive and again bigger in size.
• Low-cost products must use natural convection or conductive cooling
• Low cost packaging

Now, you should have a fair idea why reduction of power consumption is required and why every where you are listening LOW POWER – LOW POWER.

There are lots of methods and areas which are recommended or researched for low power design. Like

From Design Methodology point of view:
• Use of UPF/CPF so that you can take care of power as early as possible.
• Use of several special types of cells which can help you to reduce power (Like Isolation cell, retention cell).
• Libraries are characterized based on Threshold voltages (High Vt , Low Vt) so that it can be used as per the requirement.
• Different techniques to isolate a portion of design (if not in use).
• Divide the design as per the power requirement (Multi Voltage domain).
• Stop clocking a device/portion of design (if not in use)
• Note: it’s different from “Not providing Power” Vs “Not providing Clock”.

From Physics Point of view:
• From BJT to CMOS
• Planar FET (CMOS) to FinFet
• Reduction of Power Supply
• Frequency scaling
• Variable Threshold CMOS (VTCMOS)
• Experimenting with the Doping level /concentration
• Experimenting with the several type of Capacitance.

From Chemistry point of view:
• Use of different Metal so that Resistivity decreases (reduce power dissipation)
• Like Cu Vs Al
• Different type of Dielectric (HighK , LowK)
• Experimenting with the Gate Oxide

We will discuss all these in detail from Power point of view in next coming Articles.