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Tuesday, November 17, 2015

Low Power: Introduction

Introduction: "Why Low Power is in Demand in Semiconductor Field"

This series consists of several Article related to Low power concepts. You might be thinking that why this series because already a lot of material is present over the Net about this. And my simple Answer of this – I want to discuss all these details once again on the basis of my experience. I will try to present it in simpler language / Style which can help you to understand the concepts. I came across several articles which require some basic understanding at least. But here I will try to capture the things in such a way that anyone can understand low power concepts.
I can only try – let’s see how much I can get success. 

Very first question is why “Power is such a Big concern and need a solution”? Why everyone is talking about power and especially Low power.
Before I will explain this in more technical way, let me try it in layman language. All of us use cell phone and as the complexity/feature of the phone increases, battery backup decreases. In the market everyone is trying to get more battery backup without compromising with the Features of Cell phone. How it can be possible? Only one way is to reduce the battery consumption (power consumption) of the cell phone. Or I can say that cell phone should start functioning (in the similar fashion as before) in less power (low power consumption). That’s the reason everyone is talking about low power.
In the Semiconductor Industry, It’s a big concern. On the top of this the size of chip decrease day by day and so Power consumption is getting more and more importance. You may be thinking that if you decrease the size of the device, power consumption should also decrease. But unfortunately Power consumption is not directly proportional to size of the chip. (I will explain this in more detail later).

For higher technology nodes (may be higher than 320um), main parameters of concern were:
  • Timing
  • Area.

In the lower nodes, even after reducing supply voltages, threshold voltages (which reduce the power consumption drastically) power consumption is not in the same proportion as we were expecting. This is all because of several factors. One best example is Leakage current. The device (transistor) densities and clock frequencies also increases for lower nodes which increases power consumption. So in short there are several ways which helps to reduce the power consumption but on other side there are several factors which increase the power consumptions.
In this series, we will discuss all these things in detail.
Right now it’s very important for you to understand that power consumption levels have reached their acceptable limits (now a days) and that’s the reason power has become as important as timing or area.
So now we have 3 main parameters of concern:
  • Timing
  • Area
  • Power

(Note: In this series, we will discuss only about 3rd component - Power :).

Below are few points which will further help you to understand why now a day’s power consumption increases and why it’s important to discuss low power solutions. (These are just few points but in actual there are lots).
  • Shrinking feature Size (You might be thinking that for smaller gate the power consumption should be less then how this can be cause of high power.)
    • Gate densities have grown faster than scaling theory predicts.
      • Number of metal layers increased too
      • Wiring and gates are not scaled equally
      • Gates are not scaled equally in all dimensions
    • So overall consumption of Power increases.
    • Leakage power increases as feature sixe decreases.
  • Faster processing speeds
    • More switch On – Switch Off
    • More charging and discharging.
    • More power consumption.
  • More functionality
    • More power requirement.
  • Implementation of analog functions in digital
    • high speed, high complexity DSP
    • continuous data
  • High Die temperature
    • If power dissipation is not proper, temperature of gate/device increase
    • Lots of characteristic (like ON current) are temperature dependent. So hotter the area, more chances of fail of a chip in that area (if not taken care while designing).
    • For chip to work, output drivers need to be over-specified/characterized to guarantee drive at maximum ambient temp
    • This means increased power dissipation at all temps
  • High Power consumption increases (because of any of the above reason)
    • The temperature of the chip.
    • Sufficient heat sinks and cooling system is required which are expensive and some time bigger than the devices.
    • Reduces the battery Life. So require the bigger battery or powerful batteries which are expensive and again bigger in size.
    • Low-cost products must use natural convection or conductive cooling
  • Low cost packaging

Now, you should have a fair idea why reduction of power consumption is required and why every where you are listening LOW POWER – LOW POWER.

There are lots of methods and areas which are recommended or researched for low power design. Like

From Design Methodology point of view:
  • Use of UPF/CPF so that you can take care of power as early as possible.
  • Use of several special types of cells which can help you to reduce power (Like Isolation cell, retention cell).
  • Libraries are characterized based on Threshold voltages (High Vt , Low Vt) so that it can be used as per the requirement.
  • Different techniques to isolate a portion of design (if not in use).
  • Divide the design as per the power requirement (Multi Voltage domain).
  • Stop clocking a device/portion of design (if not in use)
    • Note: it’s different from “Not providing Power” Vs “Not providing Clock”.

From Physics Point of view:
  • From BJT to CMOS
  • Planar FET (CMOS) to FinFet
  • Reduction of Power Supply
  • Frequency scaling
  • Variable Threshold CMOS (VTCMOS)
  • Experimenting with the Doping level /concentration
  • Experimenting with the several type of Capacitance.

From Chemistry point of view:
  • Use of different Metal so that Resistivity decreases (reduce power dissipation)
    • Like Cu Vs Al
  • Different type of Dielectric (HighK , LowK)
  • Experimenting with the Gate Oxide

We will discuss all these in detail from Power point of view in next coming Articles.


  1. sir,when you are going to update this section?

  2. Can you pls update UPF section

  3. It can be nice to check more information about fet basics it will be used here.

  4. Can u give an example where isolation and retention cells are used?

  5. Hi, Can anyone please clear,
    When we use UPF file for synthesis which voltage should be mentioned (Nominal voltage or minimum voltage) in the upf file.


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