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Tuesday, February 7, 2012

Signal Integrity (SI) - Part 1

I was thinking to write over this from last 2-3 Month but unfortunately didn't get time. :( . Any ways .. lets discuss about this.

Signal Integrity is a combination of 2 words-"Signal" and "Integrity".
Signal - refers to electrical signal in electronic field. (we are talking about this defination of Signal in this blog :) )
Integrity -refers to complete and impaired or say Internal consistency or lack of corruption in electronic data.

So a digital signal with good integrity would have
  • Clean and Fast transitions
  • Stable and Valid logic levels
  • Accurate placement in time
  • Signal should be free from transition.
Now if you are clear with the above points, then its very easy to understand the whole concept behind "Signal Integrity". So lets discuss these.

Lets assume that you want to transmit a data from one location to another location. For that you want to sample the received waveform in order to obtain the binary encoded information. In a digital system, a signal is transmitted in the form of logic 1 or 0 (a certain voltage level).  For a digital component, voltage above the reference value Vih is considered as logic high, while voltage below the reference value Vil is considered as logic low.

So as I have mentioned in the starting , SI (Signal Integrity) is all about these (above) bold lines in figure.
Figure 1 (left side) shows the ideal voltage waveform in the perfect logic world, whereas Figure (right side) shows how signal will look like in a real system.

It is clear from the diagram that the data must arrive at the gate/component (which is using for sampling) on time and settle down to a non-ambiguous logic state when the receiving component starts to latch in. Any delay of the data or distortion of the data waveform will result in a failure of the data transmission.

So its important " Data should be placed accuratly in time without any delay" and "It should be clean".

Now Imagine if the signal waveform in above Figure exhibits excessive ringing into the logic gray zone while the sampling occurs, then the logic level cannot be reliably detected. Or lets assume that Signal become week/strong because of some uncertain reason and lies into the gray zone at the time of sampling.

So another important thing is "Signal  should be stable, transition free and should be of proper logic level".

One important thing- SI is not only related to VLSI domain or say Digital domain only,but its actually related to every that field where there is a transmission of waveform either in the form of Signal/Data or Electricity or anything else. That's the reason you can see this topic everywhere related to waveform propagation. e.g Radar, Microwave, RF, Satellite, VLSI, Electrical and all.

Here I am capturing few names related to SI which might you have heard during discussion with someone else related to Signal Integrity. (Note: I am not going to discuss all these in detail, but if there is any requirement then I will do my best).

Again for convience, I am going to divide this into several part.

So its divided on the following basis-
  • What are the reasons for distorting the signal. (Type of SI problem)
    • In general
    • In design
  • Where this SI problem happen.
    • In General
    • Specific area in Design. (What are the area/steps where you can do the SI analysis) 
  • Fundamental of SI
  • Modelling and Simulation of SI
  • Different type of SI tools in the market.
  • Dependent effects of SI (other problem which can be because of SI).
  • Few PT related commands or general flow.
  • Why it become so important now?
Note: I can increase these points on the requirement basis. Right Now I think all these should be sufficient for basic understanding.


  1. Have got Two new points:Clean and Fast Transitions and Stable and Valid logic.

    Looking for more on this :)

  2. please elaborate on modeling of SI

  3. Very nyc but please write all the things so that we can understand SI (g) :)

  4. insights about set up and hold time violation in DDR signals & timing wizard set up in Hyperlynx is also expected from your end.Hope you will soon publish a article waiting eagerly for your post.....

  5. Very nice and clear article. I am looking forward to hear more about SI =)

  6. HI, I have found always a great articles at vlsi-expert. Like to hear some more on SI. Please add some more info here.

  7. I’m thoroughly enjoying your blog. I too am an aspiring blog writer but I’m still new to the whole thing. Do you have any helpful hints for newbie blog writers?

  8. Highly energetic blog, I enjoyed that bit. Will there be a part 2?


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