Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

Tuesday, February 21, 2012

Design constraint : Maximum (and minimum) Capacitance

 7.4a 7.4b 7.4c Maximum Transition Time Maximum Fanout Maximum And Minimum Capacitance

Design Constraints are divided into several parts because it’s really a wide and important topic. I want to discuss this in detail. I have also noticed that lot of information is present in internet but those are bits and pieces. So I am trying my best to cover everything here in a proper way. Let me know in case any of you have any feedback.
• Part 1a ->  Basics of Design Constraints and Details of "Maximum Transition Time" (max_transition)
• Part 1b -> Maximum Fanout Constraint. (max_fanout)
• Part 1c ->  Maximum (and minimum) capacitance (max_capacitance and min_capacitance)
In the last part we have discuessed the max_fanout constraints and few details/basic of fanout in general also.
Note: Rest of the parts is still in development.
In the blog we will discuss regarding max_capacitance and min_capacitance constraints.

Maximum (and minimum) capacitance:

• The maximum (and minimum) total capacitive load that an output pin can drive.
• The total capacitance comprises of load pin capacitance and interconnects capacitances.
• This info is present in the .lib file. Please see the example with respect to one cell definition.
•  “max_capacitance” is available only for “output” pins.
•    Maximum Capacitance:
•  It is set as a pin-level attribute that defines the maximum total capacitive load that an output pin can drive.
• That is, the pin cannot connect to a net that has a total capacitance (load pin capacitance and interconnect capacitance) greater than or equal to the maximum capacitance defined at the pin.
•  This definition of max capacitance is present in the .lib file as shown in example.
•  The max_capacitance value can vary with the operating frequency of a cell. (Because the capacitive load vary as per relationship of Xc=1/ωC .)
•   It may happen that you library is characterize for multiple frequency.
•  If that‘s the case then you can see one dimensional lookup table with max_capacitance value with each driver pin for each frequency in your .lib file.
•  Minimum Capacitance:
•  Some technology libraries specify minimum capacitance.
•  The min_capacitance rule specifies the minimum load a cell can drive. It specifies the lower range of loads with which a cell has been characterized to operate.
• The load driven by a cell should meet the minimum capacitance requirement for that cell. If there is any violation then we can fix it by sizing the driver.
• This is more of a modeling constraint and has lower priority in terms of being met.
Now you can also ask why there is need/significance/importance of this parameter?

Simple Ans is – if you have more output capacitance load then it will take more time to charge /discharge to/from  a particular logic level. It means more the delay of that cell is more. So whenever you are characterization libraries then you have to take care about all this parameters. More delay – means you can’t operate this cell for faster chip. More delay mean – there are more possibility of noise. And more important is More Power consumption (dynamic power consumption – we will discuss this in more detail in other blog).

Snapshot of *.lib file (Liberty File)

cell (<cellname>) {
cell_leakage_power : 3.748077e-03;
threshold_voltage_group : "si38p" ;
area : "8.775" ;
….
abc_cell () {

pin (Z) {
direction : "output";
}
pin (CP) {
direction : "input";
}
pin (D) {
direction : "input";
}
….
}
pin (Z) {
direction : "output";
related_bias_pin : "VDDB VSSB";
max_capacitance : 0.334971 ;
max_fanout : 20 ;

timing () {
index_1 ("1.0, 1.5, 2.0") ;
values ("1.0, 1.5, 2.0") ;
}
}
pin (CP) {
clock : true;
direction : "input";
related_bias_pin : "VDDB VSSB";
rise_capacitance : 0.001733;
rise_capacitance_range(0.001268,0.002017);
capacitance : 0.001706;
fall_capacitance : 0.001680;
fall_capacitance_range(0.001293,0.001938);
max_transition : 0.550;
…..
}
}

2. waiting for cell degradation update. Good job.

3. Hello Sir,

Could you please elaborate more on importance of min_capacitance ?

1. Hi Shivaji,

2. Hello,

It will be helpful to get less delay, if a have as small capacitance as possible. then why do I need maintain a minimum capacitance. Even though it is having low priority, I just want to know the reason behind it.

3. Please elaborate the need for min capacitance.

Thanks!

4. Hi, It would very helpful if you could include explanation for cell degradataion

1. Hi,
I am really sorry that I haven't add that one till now. I will do that ASAP.

5. Although I do not know you, but I want to thank you.

6. As for the maximum capacitance, it's all clear. But, why minimum capacitance is important? Why could it not be lets say zero ?

1. valid point - but have you noticed that I have mentioned very clearly -
"This is more of a modeling constraint and has lower priority in terms of being met."

See when ever you are going to model some cell - then you have to provide a range for doing simulation. Now you can give a wide range also. But then the accuracy will not be too good.. so we usually choose a acceptable range of capacitance for modeling purpose.

But it doesn't mean that you can choose any cap below that value. If you want to use then recommendation is - use another type of cell in which you min cap comes in range.

I hope I made my point clearly. Still any confusion - feel free shoot your questions. :)

7. "has lower priority in terms of being met" - hm... as for the synthesis tools, if they don't meat DRC requirements then they do not proceed to timing optimization... So, it's not a matter of priority level since if one of the DRC rules are not fulfilled (even min capacitance) then the tools just stop all the future optimizations.
Honestly, from an electrical point of view, I still don't understand an importance of min capacitance restriction... As for max capacitance it's understood - it affect the slew rates, slops, transition time, etc... But what wrong may happen when a capacitance on the output pin of the cell is too small?

Isn't the max_capacitance limited by the Reliability Verification (RV) also? Electromigration failure will determine the maximum current your output devices can source/sink and that also determines the max_capacitance.

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25. Yeah, as other Anonymous commenter said, this is more reliability (sigem) concern than delay.

26. Would you please explain how can I fix this kind of problem that I have in my design? I have a design which is placed and routed successfully, but there are around 50 max cap violations that I do not know how to fix them. I have used focal_opt command, but it did not eliminate all these errors. The slack for max cap violation is -1.80, is that too bad? or I can ignore it?

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28. if i given onlo max tran then tool can take bobo combination and it will adguad. like wise without providing max cap also can do so whw we need provipr it

29. what exactly rise capacitance means?

30. what exactly a rise capacitance means?

31. so How can we fix the violation of max_capacitance? thanks for your help!

32. does coupling capacitance impact max capacitance?