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Monday, February 20, 2012

Design constraint : Maximum transition time

7.4a 7.4b 7.4c
Maximum Transition Time Maximum Fanout Maximum And Minimum Capacitance

Design Constraints are divided into several parts Because its really a wide and important topic. I want to discuss this in detail. I have also noticed that lot of information is present in internet but those are bits and pieces. So I am trying my best to cover every thing here in a proper way. Let me know in case any of you have any feedback.

  • Part 1a ->  Basics of Design Constraints and Details of "Maximum Transition Time" (max_transition) 
  • Part 1b ->  Maximum Fanout Constraint. (max_fanout)
  • Part 1c ->  Maximum (and minimum) capacitance (max_capacitance and min_capacitance)
  • Part 1d ->  Cell degradation (cell_degradation)
Note: Rest Of the parts are still in development.

In this blog we will discuss about the
  • Basics of Design Constraints.
  • Classification or types of "Design Constraints".
    • Design Rule Constraints
    • Optimization Constraints
  • Different type of "Design Rule Constraints".
    • Maximum transition time
    • Maximum fanout.
    • Maximum (and minimum) capacitance.
    • Cell degradation
  • Details Of Maximum Transition Time- Design Rule Constraints.
Rest of the Constraints in the next part.

First, we should know the meaning of Constraints. Constraints are type of restrictions. So if you have "N" no of ways to solve a problem, then after applying constraints it may be that there are only few solutions available. Some time it may be that there is no solution and it means the constraints are too much restrictive.
Constraints can be any type – design related, cost related, resource related and market related. But from technically point of view, as an engineer we only deal with technical constraint with in a Chip design cycle.

So Constraints are the instructions that the designer apply during various step in VLSI chip implementation, such as logic synthesis, clock tree synthesis, Place and Route, and Static Timing Analysis.  They define what the tools can or cannot do with the design or how the tool behaves.

Method of exchanging the Constraints across Different tools:  Standard Design Constraint (Synopsys Design Constraint) (SDC) format is the standard method of exchanging the design timing Constraint across different tools. (Please find the Format of SDC in the corresponding Blog).

There are basically two types of Design constraints:

Design Rule Constraints
  • Design rules constraints are defined by the ASIC vendor in the technology library (liberty file *.lib) file (implicit constraints)
  • You cannot discard or override these rules.
  • You can apply more restrictive design rules, but you cannot apply less restrictive ones. This thing you can do with the help of optimization constraints.
  • Design rules constrain the nets of a design but are associated with the pins of cells from a technology library.
  • These constraints can be library specific (common to all the cells defined in that library file) or may be individual cell specific.
Optimization Constraints
  • Optimization constraints are explicit constraints (set by the designer).
  • They describe the design goals (area, timing, and so on) the designer has set for the design.
  • They must be realistic.
Design rule constraints:

  • Maximum transition time
    • The transition time of a net is the longest time required for its driving pin to change logic values. Transition time is decided on the basis of rise time and fall time.
    • This constraint (max_transition) is based on the library data. For the nonlinear delay model (NLDM), output transition time is a function of input transition and output load.
    • Way to calculate:
      • CMOS delay model:          Transition Time = Drive R X Load C
      • Non-linear delay model: Transition Time from table lookup and interpolation/extrapolation.
    • You can make the transition time of each net less than the “max_transition” value (defined in the library file) by adding a buffer at the output of driving gate.
    • It can vary with the operating frequency of a cell.
      • Since this parameter is based on rise/fall time and rise/fall time is the time required to charge/discharge input capacitance load of the pin. Now if operating frequency vary, the capacitive load vary as per relationship of Xc=1/ωC .
    • If multiple clocks launch the same paths, the most restrictive value is used.
    • If your design uses multiple technology libraries and each has a different default_max_transition value, synthesis tools uses the smallest max_transition value globally across the design.
    • This info is present in the .lib file (liberty file). Please see the below snapshot of .lib with respect to one cell definition.
      • max_transition is available only for “input” pin.

Now there is one question – What’s the need/importance/significance of this parameter (max_transition) in the design?

Lot of people has different views for this. Like if you will increase the max_transition value then your delay will increase, so library has to characterize for those delay value also and so on. I am not saying that they are not correct but the real concept is different.

Now a day’s power consumption is becoming a major issue. Everyone wants to reduce the power consumption.
Powers are of 2 type- Switching and Leakage power. (Details we will discuss in another blog). Following structure is an inverter consisting of a p-channel to VCC and an n-channel to GND. With low-level input, the p-channel transistor is on and the n-channel is off, causing current to flow from VCC and pulling the node to a high state. With high-level input, the n-channel transistor is on, the p-channel is off, and the current flows to GND, pulling the node low. In both cases, no current flows from VCC to GND. However, when switching from one state to another, the input crosses the threshold region, causing the n-channel and the p-channel to turn on simultaneously, generating a current path between VCC and GND. This current surge can be damaging, depending on the length of time that the input is in the threshold region (Low Level threshold to High Level threshold).
Now, if the transition time is large means length of time to change the logic is large. So both the channel turns on simultaneously more time. Means more Switching power consumption. So library characterization team has to come up with a maximum value of transition time either specific to all cells in a particular library or individual cell.


So in short I can say that … When signals switch between low and high levels, there are brief periods of time in which both transistors are on. The duration of this time is proportional to the rise or fall time of the input. Long rise/fall times can cause increased current consumption and/or oscillation of the input buffer. For modern CMOS-based devices, a general rule is to transition between the Vil and Vih thresholds within about 50ns or faster.
Some devices feature a programmable input hysteresis option that allows more tolerance to slow transitioning inputs but that’s the different topic of discussion.

Snapshot of *.lib file (Liberty File)

cell (<cellname>) {
cell_leakage_power : 3.748077e-03;
threshold_voltage_group : "si38p" ;
    area : "8.775" ;
    abc_cell () {
      pin (Z) {
        direction : "output";
      pin (CP) {
        direction : "input";
      pin (D) {
        direction : "input";
pin (CP) {
      clock : true;
      direction : "input";
      related_bias_pin : "VDDB VSSB";
      rise_capacitance : 0.001733;
      capacitance : 0.001706;
      fall_capacitance : 0.001680;
      max_transition : 0.550;
pin (D) {
      direction : "input";
      related_bias_pin : "VDDB VSSB";
      rise_capacitance : 0.000752;
      capacitance : 0.000741;
      fall_capacitance : 0.000730;
      max_transition : 0.800;
      related_power_pin : "VDD";
      related_ground_pin : "VSS";

In the Next part we will discuss maximum Fanout - another type of  Design Rule Constraints.


  1. great work especially with clearing the concept of increasing transition time

  2. i have one query, Way to calculate should be more specifice

    1. Hi,
      I didn't get your point. Can you please be more specific.

  3. It's good to see this information in your post, I was looking the same but there was not any proper resource, thanks now I have the link which I was looking for my research..

    1. thanks for appreciation. Let me know in case you need any specific detail.

  4. I am still not clear with the difference between .lib files and sdc files. Design constraints are all mentioned in the .lib files. so , could you please elaborate on the use of sdc file?. i know i am missing some point here. Please elaborate.

    1. Hi,

      there are different type of constraints. Like Design Rule constraint and optimization constraint.

      You just remember a broad classification for the time being that in the .lib file - you will see only design rule constraint (no optimization constraint), and these are non-negotiable constraint.
      In sdc, you will see mostly all the optimization constraint.
      You can check the blog on the SDC also for further detail.


  5. Thank you very very much. Appreciated work.

  6. Hi,

    Really a great post.

    Can you flash some insight on, how to calculate max transition value for any design, during PnR?

  7. Thanks for the article .... will the timing constraints (setup and hold ) comes under optimization constraints ... and why designers generally considers to close timing first( to achieve required speed ?)

  8. Great article all in all , but I have a doubt , you mentioned optimization constraints are mentioned in SDC and DRC mentioned in .lib , where as in this post as well as in the "SDC" post , the same constraints are mentioned as DRC.
    Please clarify as to which ones are optimization constraints and which ones are DRC . Also please have some points on the Physical DRCs.


  9. Hi Admin,

    I am using design vision 2011.09 version, i have seen only Maximum transition time
    Maximum fanout in Design rule constraints, I would like to get the minimum transistor size in standard cell for basic inverter, But am getting larger stand cell inverter.

    How do i get the low standard cell size, for inverter i have applying Design rule constraints are Max trnasistion time.
    Maximum transition time is same for min, max size standard cell in our .lib file.

  10. Characterization software guna (from claims to determine max transition time using circuit analysis.

  11. it's really good explanation,thank you.

  12. "if operating frequency vary, the capacitive load vary..since Xc = 1/ωC"
    ω and C are the independent variables here, and do not influence each other. More to the point, frequency is applied by the user, C is determined by the fanout and changing one doesn't affect the other.

    see for what those variables mean.

    Otherwise, I learnt about the RC and NLDM models for calculating transition times, was confused and trying to integrate the two before coming to this page, thanks.

  13. Niece blog,

    I need your help here,

    You mentioned that transition time varies with frequency.

    So do you mean to say that during my Gate level simulation suppose my input frequency changes my transition time time will also changes? and if it changes what is it got violated? will it make change in my .lib file?

  14. You are giving more clarity.thank you very much.

  15. hello admin,

    whether .lib contains functionality of cells? if yes then how STA verifies timing without knowing functionality(with no stimulus), I mean functionality is known means it'll be a dynamic analysis not static.


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