Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

Tuesday, November 7, 2017

Path Base Analysis (PBA) Vs Graph Base Analysis (GBA) - part1

Today, we are going to discuss about the Path base analysis Vs Graph base analysis. As such difference is more complex compare to what I am going to explain, but right now it's sufficient to start with. :)

Let's you have a combinational path with Net delay (min, max) and Cell delay (As per the Timing Arc). If, you have any confusion with respect to the timing arc, please refer below articles.
In the below figure, you can see AND gate (1) has 2 input, so 2 set of input-output delay combination.
• Min Delay = 0.5ns, Max Delay = 1.5ns
• Min Delay = 0.2ns, Max Delay = 1.2ns
Similarly, for other logic gates.

Now, if I will ask you to calculate the delay between point A and point B, then the concept of PBA and GBA comes into the picture. Before, I explain you this concept, please refer below few figures and then see the difference between PBA and GBA.

I am sure, if you have notice closely, then you have already realized the difference. :) But still let me highlight that.

In GBA (Graph Base Analysis), in place of choosing 2 combinations of AND gate (1) delay, i.e. (Combination_1: 0.5ns, 1.5ns ; Combination_2: 0.2ns, 1.2ns) we choose extreme boundaries, i.e. min delay = 0.2ns and max delay = 1.5ns.

In case of PBA (Path base Analysis), we are using actual delay between input pin and output combination (means choosing both combination of delay).
• Combination_1: 0.5ns, 1.5ns
• Combination_2: 0.2ns, 1.2ns

Note: Check the similar difference for AND gate (2) also.

You might be thinking that this is not accurate (means why in GBA we missed 2 value), we are adding unnecessary delay in our calculation. And I am glad to say that you are right. :) The reason we are doing this because from tool point of view - doing analysis or say calculation as per GBA is very fast compare to PBA. Runtime of tool is very low. And only difference is that we are adding pessimism in our calculation.

Now, if you want to understand the calculation of delay between different input pin (A, B, C) and Output Pin (Y), please check below figures.

Note: For clarity purpose (used different color combination) - I did this calculation and pasting in the form of picture. :)

Delay Calculation in Case of GBA (Graph base Analysis).

Delay Calculation in Case of PBA (Path base Analysis).

Important observation, which you all should noticed:

Delay between A and Y
Graph base analysis (Min, Max) : 7.25ns, 10.35ns
Path base analysis (Min, Max) : 7.55ns, 10.10ns

You can see that delay between A and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA < min_delay_in_PBA
max_delay_in_GBA > max_delay_in_PBA

Delay between B and Y
Graph base analysis (Min, Max) : 7.75ns, 10.85ns
Path base analysis (Min, Max) : 7.75ns, 10.30ns

You can see that delay between B and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA = min_delay_in_PBA
max_delay_in_GBA > max_delay_in_PBA

Delay between C and Y
Graph base analysis (Min, Max) : 7.05ns, 9.05ns
Path base analysis (Min, Max) : 7.25ns, 9.05ns

You can see that delay between A and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA < min_delay_in_PBA
max_delay_in_GBA = max_delay_in_PBA

Let me summarize whole concept:
min_delay_in_GBA <= min_delay_in_PBA
max_delay_in_GBA >= max_delay_in_PBA

Now, everything is good but still you may have confusion or question - why GBA? Because from above calculation, it's not clear how it's going to save Analysis Time of a Tool. How it's beneficial for Industry? If you have all these questions, no need to worry, I will explain but not in this article. I will do that next time. But I can give you hint, so that you can think about this once.
Hint:
1) Check how these minimum and maximum delays are calculated?
2) Adding Pessimism is not an problem, it's just margin in your delay calculation. How adding margin can help us?
3) What all different environment or other factors or parameters you have to consider while calculating Delay based on different timing Arc of a gate?

I think, for now, these hints are good enough. Comment here - if you know the Answer of this, else wait for next related article. :)

BEST OF LUCK.
By - Puneet Mittal
(Founder of VLSI-Expert Group)
PBA)