## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Metal Width Variation (Part 6)

 Chapter 3: Manufacturing Effects and Their Modeling 3.1 3.2a 3.2b 3.3a 3.3b 3.3c 3.4 Introduction Effect Of Etching Process Effect Of Etching Process Chemical Mechanical Planarization Importance Of CMP process Dishing & Erosion (CMP effects) Lithography 3.5a 3.5b 3.5c 3.5d 3.5e 3.5f 3.5g Metal Width Variation (Type:1-2) Metal Width Variation (Type3) Metal Width Variation (Type:4-5) Metal Width Variation (Type6) Metal Width Variation (Type7) Metal Width Variation (Type8) Metal Width Variation (Summary)

### Width Variation Type 8:

There are few data provided by the foundry which is only effecting the Resistance or Capacitance of the design. Means there are different width variation values for effecting the Resistance and Capacitance. These type of info usually provided by 2 different tables (for any type of the variation), one specific to Resistance and other specific to Capacitance.
I know you might be thinking that how it can be possible.

Before I will explain that, it’s my duty :) wanted to remind you following thing. In design wire is long and thick (like showed in the 3D view). Length part which I am referring to is 2D view (Top View in below picture) and Thick part which I am referring to is 2D view (Front view in below picture).

In previous articles (where I have discussed about the different type of Width Variations), I have explained the width variation Type 1 to 5 using the Front-View and Variation type 6 -7 using the Top View.
Actually, in design it’s the combination of both views.

Everywhere, we are talking about the variation linearly But what about the below picture?

Yes, now we are talking about the non-uniformity in the wire itself. These non-uniformities can be introduced as part of Etching, Deposition or Lithography process. And remember, these are different from what we have discussed till now (Means variation type).

Now, if I will ask you how to model these non-uniformities, then maybe you can say that it’s very simple. Let’s take the average of this and model it as part of Width variation type. Means the calculation of the values of Bias which we are going to apply on the width should be as average value of these non-uniformities.
Your approach is 100% correct but there is catch.:0 :)You have mentioned “Average of these non-uniformities”, that’s the part I want to stress here … Average of non-uniformities in terms of which parameter? These non-uniformities have different effect on Resistance and Capacitance calculation. How? :) :)

C is more determined by outer edge of interconnect, R by average resistivity.

In case of C, when I am talking about the outer edge,
• These non-uniformities can change the distance between 2 adjacent metal wires at different point (along the length of wire), so while you are averaging the effect – may be you will consider this factor and then come up with an average biasing value which suppose to apply on width of wire.
• C is related to deposition of Charge in a plate (outer edge of plate) (we have studied this in school. There will be a lot of irregularity or say non-uniformities in the density of charge at each and every point of layer (sharp edges Vs flat edge) and if that’s the case – we have to consider that part also while doing averaging and decide a final bias value for entire edge.

In case of R
• We are more concerned about the flow of current (Means flow of electron). So mobility, drift current, effective current – these concepts comes into the picture. So while averaging these non-uniformities for R, we will consider these factor more in compare to outer distance from other metal.

You can now imagine that the same non-uniformities effects Resistance and Capacitance differently and if we want to model this – we have to divide our variation into 2 categories.
1. Width variation for Resistance.
2. Width variation for Capacitance.

Now let’s talk about one more reason of this. :) Below picture is self-explanatory (I think so). Color shades represents the metal density.

Now, may be you are thinking, why it will happen and how it will effect Resistance and Capacitance.

As, we have already discussed that interconnects are fabricated using 2 major steps
• Etching a portion of dielectric and
• then fill it up with the interconnect material.

This filling is done in different steps and somehow final material does not have uniform resistivity in cross-section (horizontal or vertical). Just because of this we have to apply different biases for R and C as a function of width.

Etching is done by bombarding loaded particles out of a plasma on the wafer surface under guidance of an electrical field. This field is not uniform but is (slightly) deformed by longer range density of the pattern and influencing etch speed. Additionally the etched away material may also influence local etching performance.
Reference: www.semiwiki.com

Variation info can be in the following way.
Note: I just took the example from variation type 1, but same concepts can be applied for other tables or other type of variation parameter also.

Table 10: Different Bias Value for Resistance and Capacitance effect
Metal Layer Width (um) Variation in % (+/-)(Resistive Only) Variation in % (+/-)(Capacitive Only)
Metal 1 0.2 8 9
Metal 2 0.4 8 9
Metal 3 0.4 9 10
Metal 4 0.4 10 11