Tuesday, February 22, 2011

Clock Reconvergence Pessimism (CRP) basic

Full Form :

CRP : Clock Reconvergence Pessimism.

What is CRP (Clock Reconvergence Pessimism)?

As the "convergence" means (dictionary) "the occurrence of two or more things coming together". So we can assume that its also related to 2 clock path coming together. (Please refer the another blog for understanding the Clock path- Static Timing Analysis Basic: Part1 "Timing Paths")

Now lets assume 2 flip-flop circuit as shown in the figure.

Clock Reconvergence Pessimism
As you can see that flop share a common clock but are placed physically at the different places in the same die. Or in other way you can say that Launch clock path and capture clock path (Please refer Static Timing Analysis Basic: Part1 "Timing Paths" for defination of Launch and Capture Clock path)  share a common segment in the clock tree till the point know as "common point" (in above fig you can see that "common point" is written as "The clock path common to both flops till this point"). The 2 clock path diverse from that point.

As we know that every cell has two type of delay as a part of its specification, "Max Delay" and "Min delay". There are several scenario in the design where we use either max delay or min delay of a particular cell. Such as best case analysis (BC), worst case (WC) analysis, OCV (on chip variation) analysis during timing analysis.

Lets consider that max delay and min delay of the common segment is as
Max delay=1.2ns
Min Delay=1.0ns.

Now, if during timing analysis a condition arise where you have to use max delay for one timing path and min delay for another timing path (such as during OCV analysis), you have to use 2 different values for a common path. But practically same set of cells can't be behave different for different clock path.

For example, for a setup check, it uses the maximum delay for the launch clock path (1.2ns + delay because of rest of the circuit in the launch path) and the minimum delay for the capture clock path (1.0ns + delay because of rest of the circuit in the launch path.

In a physical design, however, the cells along the common portion of the clock tree cannot simultaneously achieve their maximum and minimum delay values. Thus there will be a single value of delay to the common point that will be propagated to both the launching and capturing clock paths. This conflicts with our timing analysis method described above since we utilise two sets of delay values at the common point.

Therefore our timing report contains artificially introduced pessimism that is derived from our usage of max and min delay for the launching and capturing paths along this common portion of the clock network. The value of this pessimism, is the difference between max and min delay at the common point in the clock network.
 
The amount of pessimism due to this effect (in this example, 0.2 ns) is called "clock reconvergence pessimism".

Clock reconvergence pessimism = (maximum clock delay) - (minimum clock delay)


Note: Above situation is identical for hold checks also.
 
Similar type of situation can arise in different type of circuit also. Lets discuss one of that. Please see the following fig.

Schematic of a reconvergent clock
 
The two clock paths that feed into the multiplexer cannot be active at the same time, but an analysis could consider both the shorter and longer paths for one setup or hold check. This results in different launch and capture clock path delays and the consequent pessimism.

How to remove CRP ?

Automated correction of this inaccuracy is called clock reconvergence pessimism removal (CRPR). By default , most of the tools (EDA tools for timing calculation) disable this feature (automated correction). By you can enable this feature by setting one/more variables during timing analysis. Different Tools have different variable for this. For that please refer the USER GUIDE or MANUAL of corresponding tool.

11 comments:

  1. Excellent pieces. Keep posting such kind of information on your blog. I really impressed by your blog.

    ReplyDelete
  2. hi sir..Excellent explanation...
    Clock reconvergence pessimism = (maximum clock delay) - (minimum clock delay)
    Ex:Max=5,Min=2...CRP=5-2=3;(i did not understand this 3 imples what??)
    SLACk=Arrival Time-Requried Time(3(only common path of A.T)-3(common path of R.T))=0 finally common path delay not impacting on slack.)
    if i took only max(5-5) also final slack=0 or if i took min(3-3) also=0 for common pathes....why we are define this formula???

    ReplyDelete
    Replies
    1. Hi Praveen,

      First of all ... I become confuse with your figures. But I got your point... As such the solution is in the blog itself. :)

      There are 2 types of Slack- Setup Slack and Hold Slack.

      Setup Slack= required time (min) - Arrival time (max)
      so when you are calculating these delay and if there is any common path between Arrival path and Required path -- then for that common path you are calculating the dealy 2 times (1st max delay as per Arrival path ; 2nd min delay as per required time).

      So just to avoid this situation-- we have the concept of CRP.

      Please refer the STA blog for more detail regarding the calculation of setup and hold.

      I hope you get my point. Let me know in case of any confusion.

      Delete
  3. hi,
    Nice explanation. I have one doubt in CRPR.
    Suppose, If the timing path is Half-Cycle path, then how to calculate the CRPR. Can any one explain this with some suitable diagrams?

    ReplyDelete
    Replies
    1. no effect -- even if the timing path is half cycle or full cycle.
      here we are talking about the delay. Max delay and min delay of a path/cell. So this will be same whether the path is half cycle or full cycle.

      Delete
  4. sir,
    first of all thank u very much for this blog. this is very helpful for a student like me !!!!
    i hav doubt , why we need this CRPR?? The worst case will be "with out CRPR ",right? ie max delay-for launching & min delay for capturing!!!(if we set the crpr it will take only one value to the common cell delay for both launching and capturing path)
    and what will b the value of that common cell delay taken by the tool if we enable crpr?
    thanks...

    ReplyDelete
    Replies
    1. due to my understanding, the worst case will be "with out CRPR", but it will not happen in the real world. So by default we need to enable CRPR.

      When we enable CRPR, if you are running setup time check, the common cell will use max delay timing info, if you are running hold time check, the common cell will use min delay timing info. I am not sure about it, just my 2 cents. Anybody knows about it please help on this.

      Delete
  5. Hi. Amazing explanation.
    I have a qn, so can I infer that one cannot do multiple corner OCV analysis for clock paths which are converging?

    In that case most of the paths fall under the category which you explained.

    ReplyDelete
    Replies
    1. you can do that if you are doing multiple corner analysis. Point is if you are doing analysis in a specific corner and then you want to use 2 different value for a single path - we should avoid that.

      hope I am able to ans your question.

      Delete
  6. Hi,

    when i am using primetime, in report_timing report I can see this CRPR added in clock path. But this value should be removed right? or am i understanding in a wrong way? please correct me if i am wrong

    ReplyDelete

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