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Wednesday, March 16, 2011

How To Read SDF (Standard Delay Format) - Part1


To understand SDF, every one should know about the basic of Timing and different terminology/keywords related to the Timing. You can find those in my other Blogs. But here we will discuss about the SDF.

Full Form of SDF:  Standard Delay Format.

What is SDF:   SDF (Standard Delay Format) is an IEEE standard for the representation and interpretation of timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented independent of any tool and language. It includes path delays, timing constraint values, interconnect delays, high level technology parameters and etc.
The SDF specification was developed by Cadence in 1990-91, and proposed to OVI (Open Verilog International) as a standard in the same year and later modified into the IEEE format.

Tools Using this Format:  As I have mentioned above that this format is written independent of any tool, so any vendor and any tool can read this file. Any tool related to Timing analysis or verification, Any tool require delay and timing information at a particular time. E.g PrimeTime (PT) , Design Compiler (DC), IC compiler (ICC).

Information in the SDF:  As such all the timing related information and how these information should be applied by the EDA tool or by designer on a particular design can be a part of this file. Few of the information are necessary and few are optional ( detail we will discuss later). Few of the examples are...
  • Type of timing related Information
    • Delays
      • Path delay,
      • Device delay
      • Interconnect delay
      • Port delay
    • Timing checks: setup, hold, recovery, removal, skew, width, period, and nochange.
    • Timing constraints: path, skew, period, sum, and diff
    • Timing environment: intended operating timing environment
  • Ways of Implementation:
    • Incremental delays : Introduce delay data that is added to existing delay values in the design
    • Absolute delays : Introduce delay data to replace existing delay values in the design.
  • Others:
    • Conditional and unconditional module path delays and timing checks
    • Design/instance-specific or type/library-specific data
    • Scaling, environmental, and technology parameters
You can use multiple SDF files in your design. Some of the files can have pre-layout timing data, some other may have path constraint or post-layout timing data. You can create different files for different type of information or may be you can keep all the information in a single file. If you have single file, it may happen that one Tool use one particular information and another one uses other information. My point is all the tools are enough intelligent that they can extract information from the SDF file as per their requirement.

SDF files can be used for BACK-ANNOTATION and also for FORWARD-ANNOTATION. It has
  • Description of computed timing data for back-annotation.
    • An advantage of this approach is that once an SDF file has been created for a design, all analysis and verification tools can access the same timing data, which ensures consistency.
  • The specification of timing constraints for forward-annotation.
The data present in the SDF file can be generated by manually or by several available EDA tools (like Primetime). These tools are know as timing calculator. Since SDF files is just like a ASCII file and there is no separate compiler or verification tool to verify the syntax or values mention in the SDF file, So the accuracy of the data in the SDF file will be dependent on the accuracy of the timing calculator and the information made available to it, such as pre-layout interconnect estimation methods or post-layout interconnect data extracted from the device topology.

Naming Convention of SDF file: As such there is no specific naming convention of SDF files. Different EDA tools can use different extension. But usually to be more easily to identity maximum vendor use "*.sdf " as a naming style for SDF files.

Requirement of SDF: If you are preparing SDF file manually or if you are using a already written SDF file in your design, there are 2 things you have to take care.
  • Consistency between SDF file and design Description.
  • Consistency Between SDF file and timing Models.
In the absence of above Consistency, either EDA tool will give you warning/error message ( depends on capability of the tool) during reading such SDF file or extracted information may mislead you. So its user responsibility to maintain such consistency.

Please Read Next Blog for other details..


  1. Is SDF file with timing related data for all devices and nets available with us before design?? OR it is generated by EDA tool for specific design??


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