Again its not possible to explain it in a single post- so divided into multiple post. I am not sure how many of you are aware about the Hierarchical Design Flow, but now a days its very common in the Design Companies. So in short, you should be aware about the basics of this approach/flow.
Whenever we start any big work, we try to break down that work into the small-small work. In software terminology – A big program is divided into the sub-program and sub-programs into the modules (example-OOPs is based on similar approach -People those aren’t aware about this approach- skip this line).
Now, similar type of approach, when you are going to implement in the VLSI design – That Design is known as Hierarchical Design. As the size increases, complexity increases and then it become very difficult for a single person to do the routing/timing closure/ optimization etc of such a big-complex design. Apart of this there are limitation with respect to the Memory of the computer device and runtime of the EDA tools. So it is good to break/divide such a complex task into small-small task. For example, Let us suppose, you have to replace 10 4-input-AND Gates with 20 2-input-AND gates, so for that you have to load the whole design (which has almost millions of gate). So for such a small task, you have to waste a big chunk of memory.
To resolve these issues, hierarchical design methods come into picture.
The basic flow of hierarchical design is simple…
- Dividing a design into multiple blocks (sometimes referred to as sub-chips, sub-blocks, modules, hierarchical blocks, etc.).
- Designers can work on the blocks separately and in parallel from RTL through physical implementation.
- Working with smaller blocks keeps tool run-time short.
- Block-level timing closure should be relatively easy to achieve compared to the timing closure for the entire chip.
- Once all blocks are finished, they are integrated to create the final chip. Here these blocks are treated as Black-box (only few specific information available at the top level).
- Close the timing of the final chip or you can say that close the timing between the blocks. If proper work has done in the starting, it should be close in first iteration (Ideally).
Pictorial view of the Hierarchy based Design Flow is as … (Source: EEtime)
In the above fig we have mentioned 2 types of hierarchy.
- Physical Hierarchy: Physical hierarchy is based on back-end considerations such as cell placement, I/O placement, macro placement, interconnect routing and associated timing issues.
- Logical Hierarchy: Based on the function of the design modules/blocks, which is usually determined by the designers and their HDL coding methods.
These 2 are different but still there should be a correlation between these 2 so that we can reduce the time needed to achieve the timing of the chip.
Hierarchical design Flow benefits:
- Improved Productivity when designing complex chips.
- Run time is fast because you can work over individual block and those will be small in size in comparison to the full design.
- In case of any timing issue, you can fix individual block.
- Incremental functional and timing fixes is possible after timing closure.
In the traditional flat ASIC flow,
- If there is any problem in the timing after routing, then there are equal chances that you have to go back to the architecture level design for correcting that.
- Memory limitation can also create problem
- Run time in the case of multi-million gate design is huge.
One thing keep in mind, I am not saying that Full-flat design is useless or Hierarchical design has replaced that approach completely. But Hierarchical design offloads the burden of Full-flat flow (traditional flow) during the implementation phase. Even now, at the signoff stage, most of the companies (even I can say 99% companies) are using Full-flat-flow for rechecking everything and to make sure nothing is messed up in between. But after using hierarchical approach, even in implementation phase, designers have saved a significant time.
Now if you pay attention, you come to know that as per the pictorial diagram, there is only 1 important step in the Hierarchical flow and that is the “Setting block level constraints”.
Block Level Constraints are of 2 types:
- Physical Constraint: These constraints depend on the floor-plan of the top level. Means where exactly this block will be placed on the top level.
- Size and shape of the block
- Pin placement with in the block
Always remember that these constraints can’t be decided in a single iteration. For setting these constraints we have to use both the top-down and bottom-up approaches. Like position of the pin in the block depends on the position of the pins required in the final chip. In the similar way, if there is any hard macro (you can’t change the position of the pin in that), so you have to place that block in such a way that it should be closer to the pin position of the final chip. So in the complex design with large number of blocks, you have to do few iteration and you have to use both the approaches in parallel.
During deciding these constraints, in most of the cases we add enough margins so that we can cover any inaccuracy in estimating (which we have done in early phase of the design) at the end of design cycle.A uniquely identifiable element.
List of physical constraints are: (it contain all the top level and block level constraints)
- Die area
- Core Placement area
- Aspect Ratio
- Port side
- Port Location
- Cell location
- Pin Location
- Placement Blockage
- Wiring keepout
- Voltage Area
- Site Row
If you have notice, all physical constraints are related to the location. It’s like when you are designing a layout of your house, then you are applying a lot of constraints like window should be in left, door should be in North, some corner is fixed for Kitchen. So similarly in chip designing, you have to place a lot of constraints as per the requirement/specification of the chip or sometime as per the specification of the IP blocks.
In the next part we will study about the Timing Constraint.