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Monday, July 30, 2012

Static Timing Analysis (STA) Using EDA Tool - Part2



5.1 5.2
STA Using EDA tool (Part1) STA Using EDA tool (Part2)

In the last article (Static Timing Analysis using EDA Tool), we have discussed the type of data required for STA analysis. What all type of analysis we can do as per the specification. We have mentioned in last blog also that here we will discuss (STA analysis) keeping EDA tools in our mind.

Now, we know that what all  data are required but before using these data we should know where exactly we need these data in the Timing analysis. I mean to say, Design Cycle has been divided into Pre-Layout and Post-Layout broadly. First of all we should know where (in terms of Step/Sequence/Area) exactly, we are doing Timing Analysis in Pre-Layout Design and Post-Layout design. Once that’s figure out then we will Study about the typical STA Flow.
This will help us to know, that the type of data which I have mentioned in the last part is really required or not. And if its required then practically how we can use it during the STA analysis.

In case of Pre-layout design the Typical Flow is

Pre-layout Typical STA Flow

In case of Post-layout Design, Typical Flow is

Post-Layout Typical STA Flow

So overall, I can say that STA has been performed after every major step ( Synthesis/ Floorplanning/ CTS / Place and Route)  in the design cycle. Now it’s not necessary that you will get all the mentioned data (in the last blog) in their respective format at each and every step. Like If your design is not routed (no place and route step), no Physical wire available at that point, you can’t get exact net-delay in the form of SPEF. And even if you have SPEF, it will not have exact net-delay information. It doesn’t mean that you can’t perform STA; you can do that by using alternative way. You can use wire load model or SDF in place of SPEF.

So there maybe lot of such scenario in your design, but still you can perform STA. That’s the different thing that those results will not be accurate but those can help you to identify/rectify any surprises in the starting itself. You can fix those issues, so that you can ignore/reduce the number of iteration of coming back and fixing issues. Even EDA tools are enough intelligent or say that so much flexible that they will provide you several options to deal such situation.

Let’s have a look to the sample script in case of PrimeTime. (Same script you can use for ETS also,just you have to replace the corresponding commands in the flow.

********************************
** Prime Time Sample Script Start **
********************************

## Define the variable corresponding to scripts directory, output reports, saved session directories and environment settings
set script_dir /abc/cde/scripts
set report_dir /abc/cde/rpts
set save_session_dir /abc/cde/save_sessions
set log_dir /abc/cde/logs
…..
…..

# # Initialize Design Variables related to SI, AOCV/OCV setting

set si_enable_analysis false
……
set timing_crpr_threshold_ps 20
…….
set auto_wire_load_selection false
…….
set_timing_derate -late 1.65
set_timing_derate -early 0.93

## Define variables to load Library and design Data

set SDC  vlsi_expert_design.sdc
set corner slow_m40_0p85_cworstspef
set NETLIST_DIR /abc/cde/netlist
set SPEF_DIR /abc/cde/spefs
set enable_aocv false
set search_path /abc/cde/libraries
set logic_libs [list buffer sp_buffer hvt_lib rvt_lib … ]
set io_libs [list ….]
set general_libs [ list …]

set top_design_name vlsi_expert_design

## Set other design Specific setting like Operating condition name, Clock Uncertainty for setup and hold,
…..
…..

##  read and link the design and then read other necessary file/input data.

read_verilog $NETLIST_DIR/vlsi_expert.v
link
source $SDC
read_parasitics $SPEF_DIR/ vlsi_expert.spef

## if SI is enable, replace the above command with below commad.
## read_parasitics -keep_capacitive_coupling $SPEF_DIR/ vlsi_expert.spef

## Performs timing analysis
update_timing –full

save_session $save_session_dir/vlsi_save_session

## Perform a full analysis and examine different type of results
report_timing > $report_dir/timing.rpt
report_constraint ;          > $report_dir/constraint.rpt
report_bottleneck > $report_dir/bottleneck.rpt
….
…..



********************************
** Prime Time Sample Script END ***
********************************

So now you have a template and it will help you to write any Primetime related script for your design. If you are using any other EDA tool, then you have to just find out the corresponding commands, everything else be the same.
Taking the above template as a reference, you can see that whole Timing analysis is divided into 5 major steps. Please find those steps in terms of PrimeTime ..

Static Timing Analysis Flow (Prime-Time as a reference)

STEP1: Read the design data.

set search_path
set link_path
read_db
read_verilog
link_design
read_sdf
read_parasitics

Note:
  • The search_path variable specifies a list of directories from where tool can read the design and library files, so that you do not need to specify a full path each time you read in a file. There is no need to define this path if you are specifying absolute path.
  • The link_path variable specifies where and in what order Prime-Time looks for design files and library files for linking the design. For example,

pt_shell> set search_path ". /u/proj/design /u/proj/lib"
pt_shell> set link_path "* STDLIB.db"


STEP2: Constraint the design.

create_clock
set_clock_uncertainty
set_clock_latency
set_clock_transition
set_input_delay
set_out_put_delay

Note: This is usually the part of SDC. But some time if you want to define any extra constraint, you can use it.

STEP3: Specify the environment and analysis conditions

set_operating_conditions
set_case_analysis
set_mode
read_sdf
read_parasitic
set_driving_cell
set_load
set_wire_load_model
set_multicycle_path
set_false_path
set_disable_timing

Note: These are the setting which may vary based on the type of analysis you want to do. As I have mentioned in my last blog that you can perform a number of analysis (please refer previous blog), so to perform those analysis, you have to make the changes in these type of variables. Most of the time designer has if-else loop on the basic of analysis before setting proper value to these variables.

STEP4:  Check the design and analysis setup (Reporting Commands)
check_timing  
report_design               >> It will give you all the information about your design
report_port                  >> All the ports in your design
report_net                    >> Give you all the result regarding all the nets in your design.
report_cell                   >> It will tell you how many cells are present and whether they are connected as per your design.
report_wire_load
report_path_group
report_clock                 >> with the help of this you can check whether everything is correct in terms of clocks. (Means you have created a clock .. whether that is created as per your wishes or not.)
report_hierarchy 
report_reference
report_lib 


Note:  There are several other commands. You can insert as many commands in your run/script, but these commands effects your runtime. So, only use those command in the script which are necessary and keep rest for debugging purpose, in case there is any problem.

STEP5: Perform a full analysis and examine the results

report_timing
report_constraint
report_bottleneck
report_analysis_coverage
report_delay_calculation
update_timing

These were the steps ( definitely not in sequence). You can say that there are few overlaps but that's okay. My intention is not to make you PrimeTime/ETS expert, I just want to make you aware about the flow using EDA tools. :)

Now in the next post we will discuss more about the data. Like which data is necessary and which can be optional. In the lack of which data you will not be able to run the EDA tool and in which case you will get less accurate results.

Please keep me posted in case you have any doubt in this specific post.





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